High Throughput/Gate AES Hardware Architectures Based on Datapath Compression

Abstract

This article proposes highly efficient Advanced Encryption Standard (AES) hardware architectures that support encryption and both encryption and decryption. New operation-reordering and register-retiming techniques presented in this article allow us to unify the inversion circuits in SubBytes and InvSubBytes without any delay overhead. In addition, a new optimization technique for minimizing linear mappings, named multiplicative-offset, further enhances the hardware efficiency. We also present a shared key scheduling datapath that can work on-the-fly in the proposed architecture. To the best of our knowledge, the proposed architecture has the shortest critical path delay and is the most efficient in terms of throughput per area among conventional AES encryption/decryption and encryption architectures with tower-field S-boxes. The proposed round-based architecture can perform AES encryption where block-wise parallelism is unavailable (e.g., cipher block chaining (CBC) mode); thus, our techniques can be globally applied to any type of architecture including pipelined ones. We evaluated the performance of the proposed and some conventional datapaths by logic synthesis with the NanGate 45-nm open-cell library. As a result, we can confirm that our proposed architectures achieve approximately 51-64 percent higher efficiency (i.e., higher bps/GE) and lower power/energy consumption than the other conventional counterparts.

On-the-Fly Parallel Processing IP-Core for Image Blur Detection, Compression, and Chaotic Encryption Based on FPGA

“…The compression performance of the system is assessed by calculating the Peak Signal-to-Noise Ratio (PSNR) versus the Compression Ratio (CR). The CR is calculated as shown in (5). The PSNR is calculated as shown in (6a), (6b), and (6c) where MSE is the Mean Square Error, M×N is the dimensions of the image, f1(x,y) is the plain image, and f2(x,y) is the reconstructed image.…”

“…The Advanced Encryption Standard (AES) is an ISO/IEC 18033-3:2010 standard for symmetric block cipher. The AES is one of the most powerful encryption standards, and it has been used in a lot of protocols, such as the IEEE802.11 wireless Local Area Network (LAN) and the IEEE802.15.4 wireless sensor networks [5]. The AES encryption has been frequently used in the Cipher Block Chaining (CBC) mode, which needs a Pseudo Random Number Generator (PRNG) to generate the Initialization Vector (IV).…”

IMCRYPTO: An In-Memory Computing Fabric for AES Encryption and Decryption

“…One of the strategies to minimize area without compromising performance is to re-use circuit blocks and to design shared datapaths for encryption and decryption [4], [22]. In this regard, [4] introduces an architecture for AES with shared encryption/decryption datapaths.…”

“…We have performed detailed circuit-level, simulation-based evaluations of our proposed IMCRYPTO architecture. We consider figures of merit such as delay, area, power, throughput, area-delay-power product (ADPP), and throughput per area and compare them with state-of-the-art ASIC and IMC-based accelerators for AES encryption [4]- [7]. Results indicate minimum (maximum) throughput per area improvements of 3.3× (223.1×) and minimum (maximum) ADPP improvements of 1.2× (6,238.3×) for CMOS-based IMCRYPTO when compared to ASIC and IMC accelerators for AES-128 encryption of a 1MB plaintext.…”

Physical Attack Protection Techniques for IC Chip Level Hardware Security

“…Symmetric ciphers are often preferred in the communications of data and control codes since their encryption and decryption are attained at sufficiently high processing throughputs with a relatively smaller number of transistors. The advanced encryption standard (AES) [1] is the most popularly adopted and pursued for performance with integrated circuit (IC) technologies [2], [3] or even with field-programmable gate array (FPGA) devices [4], [5]. Also, a variety of lightweight ciphers has been developed [6] and evaluated in IC-chip Makoto Nagata and Takuji Miki are with the Graduate School of Science, Technology and Innovation, Kobe University, Kobe 657-8501, Japan (e-mail: nagata@cs.kobe-u.ac.jp).…”