A 1.5-V full-swing bootstrapped CMOS large capacitive-load driver circuit suitable for low-voltage CMOS VLSI

Lou, J.H.; Kuo, Jing-Lin

doi:10.1109/4.553191

Cited by 68 publications

(31 citation statements)

References 3 publications

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“…The bootstrapped CMOS driver in [8] provides a short turn-on delay for faster speed. It, however, requires almost 2X transistor counts compared with the conventional bootstrapped driver in [3] and has larger parasitic capacitance at the charge sharing gate nodes of the output driver devices, resulting in more power dissipation and degraded boosting efficiency. The bootstrapped driver in [9] requires four capacitors, twice that of the conventional bootstrapped driver and, hence, a large area overhead.…”

Section: Introductionmentioning

confidence: 99%

“…However, reducing supply voltage causes a substantial speed penalty, since the drain-source voltage and gate-source voltage of CMOS transistors are simultaneously reduced, leading to significant degradation of driving current and switching speed. Conventional bootstrapped CMOS driver [3].…”

Section: Introductionmentioning

confidence: 99%

“…In order to drive a large distributed RC-load, the design of an energy efficient driver circuit has become a critical concern for switching speed and power consumption. Since the threshold voltage of a CMOS device cannot be easily scaled down with supply voltage, the design of an energy efficient high-performance driver operating at a low supply voltage (or subthreshold voltage level) poses a significant challenge [3][4][5]. A bootstrapped CMOS driver circuit [3] (shown in Figure 1) was proposed previously.…”

Section: Introductionmentioning

confidence: 99%

“…Since the threshold voltage of a CMOS device cannot be easily scaled down with supply voltage, the design of an energy efficient high-performance driver operating at a low supply voltage (or subthreshold voltage level) poses a significant challenge [3][4][5]. A bootstrapped CMOS driver circuit [3] (shown in Figure 1) was proposed previously. This driver mainly consists of positive and negative voltage bootstrapped circuits and a pair of corresponding driver transistors (MP1 and MN1).…”

Section: Introductionmentioning

confidence: 99%

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Energy Efficient Bootstrapped CMOS Large RC-Load Driver Circuit for Ultra Low-Voltage VLSI

Chuang

2012

JLPEA

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This paper presents an energy efficient bootstrapped CMOS driver to enhance the switching speed for driving large RC load for ultra-low-voltage CMOS VLSI. The proposed bootstrapped driver eliminates the leakage paths in the conventional bootstrapped driver to achieve and maintain more positive and negative boosted voltage levels of the boosted nodes, thus improving boosting efficiency and enhancing driver switching speed. Measured performance from test chips implemented with UMC 65 nm low-power CMOS technology (VTN ≈ VTP ≈ 0.5 V) indicates that the proposed driver provides a rising-delay improvement of 37%-50% and a falling-delay improvement of 25%-47% at 0.3 V for a loading ranging from a 0 to 24 mm long M6 metal line compared with the conventional bootstrapped driver. Although designed and optimized for subthreshold ultra low-voltage operation, the proposed bootstrapped driver is shown to be advantageous at higher nearly-threshold supply voltage as well. The proposed driver provides a rising delay improvement of 20% to 52% and a falling delay improvement of 23%-43% for VDD ranging from 0.3 V to 0.5 V, while consuming about 15% less average power than the conventional bootstrapped driver driving a 16 mm long M6 wire.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Energy Efficient Bootstrapped CMOS Large RC-Load Driver Circuit for Ultra Low-Voltage VLSI

Chuang

2012

JLPEA

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“…To allow digital CMOS circuits to operate fast at scaled supply voltages, the bootstrapped CMOS large capacitive-load driver [4] was proposed. It can improve the switching speed of the driver at low supply voltages by allowing the voltage of internal nodes to be boosted beyond the supply rails.…”

Section: Introductionmentioning

confidence: 99%

Novel bootstrapped CMOS differential logic family for ultra-low voltage SoCs

Jung

Kang

et al. 2008

IEICE Electron. Express

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This paper describes novel bootstrapped CMOS logic family operating at ultra-low supply voltages. The proposed logic family provides better switching performance than conventional bootstrapped logic family by isolating the bootstrapping circuit from timing-critical signal paths. The logic family also minimizes area overhead due to the bootstrapping circuit by adapting a differential structure having a single bootstrap capacitor shared between complementary outputs. Multi-input XOR/XNOR gates and 64-bit adders were designed in 0.18 um CMOS process as test vehicles for assessing the performance. Comparison results indicate that the power-delay product of the proposed logic family is improved by up to 67% compared to conventional differential logic circuits at the supply voltage ranging from 0.5 V to 0.8 V. Solid-State Circuits, vol. sc-17, no. 3, pp. 614-619, June 1982. [4] J. H. Lou and J. B. Kuo, "A 1.5 V full-swing bootstrapped CMOS large capacitive-load driver circuit suitable for low-voltage CMOS VLSI," IEEE J. Solid-State Circuits, vol. 32, no. 1, pp. 119-121, Jan. 1997. [5] J. H. Lou and J. B. Kuo, "A 1.5-V CMOS all-N-logic true-single-phase bootstrapped dynamic-logic circuit suitable for low supply voltage and high-speed pipelined system operation," IEEE Trans.

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