Novel bootstrapped CMOS differential logic family for ultra-low voltage SoCs

Abstract

This paper describes novel bootstrapped CMOS logic family operating at ultra-low supply voltages. The proposed logic family provides better switching performance than conventional bootstrapped logic family by isolating the bootstrapping circuit from timing-critical signal paths. The logic family also minimizes area overhead due to the bootstrapping circuit by adapting a differential structure having a single bootstrap capacitor shared between complementary outputs. Multi-input XOR/XNOR gates and 64-bit adders were designed in 0.18 um CMOS process as test vehicles for assessing the performance. Comparison results indicate that the power-delay product of the proposed logic family is improved by up to 67% compared to conventional differential logic circuits at the supply voltage ranging from 0.5 V to 0.8 V. Solid-State Circuits, vol. sc-17, no. 3, pp. 614-619, June 1982. [4] J. H. Lou and J. B. Kuo, "A 1.5 V full-swing bootstrapped CMOS large capacitive-load driver circuit suitable for low-voltage CMOS VLSI," IEEE J. Solid-State Circuits, vol. 32, no. 1, pp. 119-121, Jan. 1997. [5] J. H. Lou and J. B. Kuo, "A 1.5-V CMOS all-N-logic true-single-phase bootstrapped dynamic-logic circuit suitable for low supply voltage and high-speed pipelined system operation," IEEE Trans.