A 1.0625-to-14.025Gb/s multimedia transceiver with full-rate source-series-terminated transmit driver and floating-tap decision-feedback equalizer in 40nm CMOS

Quan, Shaolei; Zhong, Freeman; Liu, Wing; Aziz, P.M.; Jing, Tai; Dong, Jen; Desai, C. F.; Gao, Hongli; Garcı́a, M. Esther; Hom, Gary J.; Huynh, Tony; Kimura, Hiroshi; Kothari, Ruchi; Li, Lijun; Liu, Cathy; Lowrie, Scott; Ling, Kathy; Malipatil, Amaresh; Narayan, Ram; Prokop, Tom; Palusa, Chaitanya; Rajashekara, Anil; Sinha, Ashutosh Kumar; Zhong, Charlie; Zhang, Eric

doi:10.1109/isscc.2011.5746348

Cited by 5 publications

(3 citation statements)

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“…The multi-rate serial link data transmitter (MRTX) [1,2] is attractive in industry because it is compatible for both new link standards and legacy systems. In the MRTX, the wideband low-jitter phase-locked loop (PLL) is one of the most critical building blocks.…”

Section: Introductionmentioning

confidence: 99%

A 1.25-to-6.25 GHz −237.2-dB FOM wideband self-biased PLL for multi-rate serial link data transmitter

Zhang

Yang

Liu

et al. 2017

IEICE Electron. Express

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This paper proposes wideband low-power low-jitter self-biased phase-locked loop (SBPLL) for multi-rate serial link transmitter application. It adopts a proposed low-power source-degeneration voltage-to-current converter not only to save power but also to reduce the phase noise contributed by the voltage-to-current converter. The proposed SBPLL is implemented in a 65-nm CMOS process, and the active core area is 0.01 mm 2 . Measurement result shows that the SBPLL can generate clock with frequency from 1.25 to 6.25 GHz and the loop bandwidth can be kept around 20 MHz regardless of the output frequency. The rms jitter integrated from 10 kHz to 300 MHz is 780 fs at carrier frequency of 6.25 GHz and maximum power efficiency is 0.496 mW/GHz with 1.2-V supply. The figure-of-merit (FOM) is −237.2 dB. The measurement results also show good robustness of the SBPLL over temperature and supply voltage variation.

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Section: Introductionmentioning

confidence: 99%

A 1.25-to-6.25 GHz −237.2-dB FOM wideband self-biased PLL for multi-rate serial link data transmitter

Zhang

Yang

Liu

et al. 2017

IEICE Electron. Express

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“…To find the values of Rp1, Rp2, Ic1, Rc1 and Rc2 automatically, a 16b pulse pattern (1000…000) is repeated during the training mode. This approach is simpler than the SS-LMS algorithm [3].…”

mentioning

confidence: 99%

A 27% reduction in transceiver power for single-ended point-to-point DRAM interface with the termination resistance of 4×Z<inf>0</inf> at both TX and RX

Lee

Kim

et al. 2013

2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers

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The transceiver power is reduced by 27% in the single-ended point-to-point DRAM interface by increasing the termination resistance to 4×Z 0 at both ends of TX and RX. The resultant increase of ISI and reflection is compensated for at RX by using the 1-tap and 2-tap integrating decision-feedback equalizer (IDFE), respectively, where the reflection tap position and the tap coefficients are found automatically during the training mode. This improves the bathtub opening of a 4-inch FR4 channel from 20% to 62.5% at 5Gb/s in 0.13μm CMOS.As the data rate for the chip-to-chip interface of DRAM reaches several Gb/s, the I/O interface circuit consumes around 20 to 30% of the total chip power. Recently, there is a strong demand for low power in the mobile DRAM interface without reducing the data rate. In the DRAM interface with the single-ended signaling, the output driver dominates the power consumption. However, the output driver power is almost fixed because of the termination requirements at both TX and RX as well as the fixed signal swing. The pseudo open drain (POD) driver ( Fig. 17.2.1) is usually used as output driver in the DRAM interface [1,2]. The output voltage swing cannot be reduced significantly because of the environmental noise and input offset voltage at RX. In the POD driver, the output voltage swing is fixed at 0.5V DD (V DD -0.5V DD ), where the energy per bit spent by output driver is 0.5V DD 2 (0.25C T + 0.5T/R T ), where C T is the total capacitance of transmission channel including the chip pin capacitance and T is the data period. It assumes the equal probability for data '1' and '0'. If the termination resistance R T is fixed at Z 0 (characteristic impedance of transmission line), the energy per bit of output driver is fixed. In this work, R T is deliberately increased to 4×Z 0 to reduce the output driver power. This increases both ISI and reflection, which are compensated for at RX by using the IDFE circuit with 2 taps for reflection and 1 tap for ISI. For the write operation into DRAM chips, the IDFE circuit must be implemented in DRAM. This is an overhead in DRAM. However, with the scaled down technology, the area and power consumption of IDFE will be reduced further.The single-pulse response and eye-diagram for R T = Z 0 and R T = 4×Z 0 are shown in Fig. 17.2.1 at 5Gb/s for a 4-inch FR4 channel. For R T = 4×Z 0 , the amplitude of main pulse is reduced by 0.64 and the significant increase of reflection and ISI can be observed. To compensate for the ISI and reflection using the 3-tap IDFE circuit at RX, we need the IDFE tap positions (Rp1, Rp2) corresponding to the reflection point as well as the IDFE coefficients for ISI (Ic1) and reflection (Rc1, Rc2). While the ISI occurs during the data period next to the main pulse, the reflection point occurs after 2t f from the main pulse, where t f is the time of flight of the transmission channel. The IDFE tap position for reflection point from the main pulse is determined by the product of 2t f and the data rate. To find the values of Rp1, Rp2, Ic1, Rc...

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“…1b, in which the first tap is taken out of the critical path by having two comparators in parallel. However, this is achieved at the cost of the added multiplexer (MUX) delay and doubled C L , which in turn increase the overall required A 1 v BW 1 at the summing node [4]. Hence, considering channels with different first post-cursor h 1 (or equivalently the weight of the first DFE tap, t 1 ), this approach does not necessarily decrease the DFE's power penalty or enhance the timing margin.…”

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confidence: 99%

Low-power design technique for decision-feedback equalisation in serial links

Zargaran-Yazd

Mirabbasi

2012

Electronics Letters

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A design technique for performing low-power decision-feedback equalisation for multi-Gbit/s serial links is presented. The technique systematically reduces the capacitive loading on the timing-critical node within the feedback loop of the equaliser. Based on the proposed technique, an architecture capable of both equalisation and digitisation of the received data is presented. Power efficiency of the proposed architecture is analysed and is compared with that of conventional analogue and loop-unrolled decision-feedback equalisers. The technique is validated through a proof-of-concept chip fabricated in 65 nm CMOS.Introduction: Decision-feedback equalisers (DFEs) it are a key component of high-data-rate, e.g. the emerging 40 to 100 Gbit/s, wireline receivers (RXs) [1]. In channels with a long impulse response tail, cancelling the post-cursor inter-symbol interference (ISI) using a DFE is a preferred choice over using a feed-forward equaliser (FFE). Such design choice is based on the fact that unlike FFEs, DFEs do not enhance the noise, or deliberately attenuate high-frequency components of the received signal [2]. However, DFEs suffer from a stringent requirement for timing closure within a 1 unit interval (UI) in the feedback loop. Depending on the speed and the required amount of post-cursor ISI cancellation, the power consumption of the DFE block may exceed the receiver's power budget [3]. Furthermore, given a CMOS technology, the implementation of high-speed DFEs may not be feasible due to capacitive self-loading of devices. In this Letter, we propose a DFE implementation technique that relaxes the trade-off among the power consumption, the data rate, and the amount of post-cursor ISI needed to be cancelled.

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A 1.0625-to-14.025Gb/s multimedia transceiver with full-rate source-series-terminated transmit driver and floating-tap decision-feedback equalizer in 40nm CMOS

Cited by 5 publications

References 5 publications

A 1.25-to-6.25 GHz −237.2-dB FOM wideband self-biased PLL for multi-rate serial link data transmitter

A 1.25-to-6.25 GHz −237.2-dB FOM wideband self-biased PLL for multi-rate serial link data transmitter

A 27% reduction in transceiver power for single-ended point-to-point DRAM interface with the termination resistance of 4×Z<inf>0</inf> at both TX and RX

Low-power design technique for decision-feedback equalisation in serial links

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A 1.0625-to-14.025Gb/s multimedia transceiver with full-rate source-series-terminated transmit driver and floating-tap decision-feedback equalizer in 40nm CMOS

Cited by 5 publications

References 5 publications

A 1.25-to-6.25 GHz −237.2-dB FOM wideband self-biased PLL for multi-rate serial link data transmitter

A 1.25-to-6.25 GHz −237.2-dB FOM wideband self-biased PLL for multi-rate serial link data transmitter

A 27% reduction in transceiver power for single-ended point-to-point DRAM interface with the termination resistance of 4&#x00D7;Z<inf>0</inf> at both TX and RX

Low-power design technique for decision-feedback equalisation in serial links

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A 27% reduction in transceiver power for single-ended point-to-point DRAM interface with the termination resistance of 4×Z<inf>0</inf> at both TX and RX