A 1.25-to-6.25 GHz −237.2-dB FOM wideband self-biased PLL for multi-rate serial link data transmitter

Zhang, Zhao; Yang, Jincheng; Liu, Liyuan; Feng, Peng; Liu, Jian; Wu, Nanjian

doi:10.1587/elex.14.20170422

Cited by 6 publications

(6 citation statements)

References 7 publications

(3 reference statements)

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“…When the tuning range is divided into several sub-bands, the tuning range is widened and Kvco should be reduced to optimize the phase noise. However, PLL synthesizer bandwidth affects most of those parameters directly or indirectly [7,8,9,10,11,12,13,14]. A lower loop bandwidth suppresses the in-band phase noise but extend the settling time.…”

Section: Introductionmentioning

confidence: 99%

Design of a constant loop bandwidth phase-locked loop based on artificial neural network

Guo

et al. 2021

IEICE Electron. Express

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An LC-VCO based phase-locked loop (PLL) frequency synthesizer which incorporates loop bandwidth tracking technique based on neural network is presented in this work. In order to minimize loop bandwidth variations, the proposed PLL employs an averaging varactor based split-tuned LC-VCO and a controllable phase error scaling module. Biasing voltages of varactor and the control word of the phase error scaling module are trained by the neural network and updated. The proposed technique can maintain a constant loop bandwidth over operating frequencies from 1.6-2GHz with variation varying from −2.66∼3%.

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Section: Introductionmentioning

confidence: 99%

Design of a constant loop bandwidth phase-locked loop based on artificial neural network

Guo

et al. 2021

IEICE Electron. Express

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“…There are mainly two kinds of phase-locked loop (PLL) to realise the WBFS: the Ring-VCO based PLL (RPLL) and the LC-VCO based PLL (LCPLL). The RPLL can easily cover wide frequency range from several tens of megahertz to several gigahertz [1][2][3], but its main drawback is its poor phase noise performance. In addition, the large tuning gain of the ring VCO leads to high spur level and high phase noise level contributed from loop filter.…”

Section: Introductionmentioning

confidence: 99%

0.1–5 GHz wideband ΔΣ fractional‐N frequency synthesiser for software‐defined radio application

Zhang

Yang

Liu

et al. 2019

IET Circuits, Devices & Systems

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This article proposes a wideband ΔΣ fractional-N frequency synthesiser (WBFS) for software-defined radio application. The frequency synthesiser has two modes: the regular mode with low phase noise performance and the low-power mode for the low-power applications at lower frequency band. The authors also propose adjustable replica (AR) bias circuit for the frequency selection multiplexer (FSMUX) in the divide-by-two divider chain to optimise the power consumption at different frequencies while keep the output swing constant at different bias current to achieve robust operation. The FSMUX is implemented in differential structure instead of the widely used quadrature structure to reduce power and area especially at high carrier frequency. Implemented in 65 nm CMOS process with a 1.2-V supply, the WBFS generates frequency from 0.1 to 5 GHz. The maximum power at regular and low-power mode is 21 and 10.2 mW, respectively. The phase noise is −120.3 dBc/Hz at 1 MHz offset (2.75375 GHz) at regular mode and −122.8 dBc/Hz at 1 MHz offset (1.3525 GHz) at low-power mode. Thanks to the differential FSMUX with the proposed AR bias circuit and the low-power mode, the WBFS power is significantly reduced, compared with that of the prior WBFS with comparable frequency range.

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“…Among analog PLLs, SPLLs have been widely investigated as their good performance. To reduce power consumption and phase noise, a low-power source-degeneration voltage-to-current converters is adopted in [1]. However, the lock time is not improved because its loop bandwidth cannot scale with the input frequency.…”

mentioning

confidence: 99%

A Wideband PLL with Adaptive Fast-Locking Current Circuit for Bandwidth Tracking and Settling Time Reduction

Wang

Shu

Yang

2023

Preprint

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This letter presents a 1-3GHz low-power, fast-locking self-biased phase-locked loop (SPLL) for multiprotocol SerDes applications. The PLL realizes adaptive bandwidth tracking based on fast-locking current injection, which accelerates loop acquisition and maintains reduced settling time across a wide frequency range. Additionally, a start-up module is adopted to reset the system quickly to an optimal initial operating frequency. The proposed PLL, fabricated in TSMC 28-nm CMOS process and occupies a compact 0.028mm2 area. It achieves a roughly constant settling time of 5 μs over all frequencies and division ratios range. Compared with the typical SPLL, the measured settling time can be shortened about 85% large division ratios.

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A 1.25-to-6.25 GHz −237.2-dB FOM wideband self-biased PLL for multi-rate serial link data transmitter

Cited by 6 publications

References 7 publications

Design of a constant loop bandwidth phase-locked loop based on artificial neural network

Design of a constant loop bandwidth phase-locked loop based on artificial neural network

0.1–5 GHz wideband ΔΣ fractional‐N frequency synthesiser for software‐defined radio application

A Wideband PLL with Adaptive Fast-Locking Current Circuit for Bandwidth Tracking and Settling Time Reduction

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