2019
DOI: 10.1049/iet-cds.2018.5271
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0.1–5 GHz wideband ΔΣ fractional‐N frequency synthesiser for software‐defined radio application

Abstract: This article proposes a wideband ΔΣ fractional-N frequency synthesiser (WBFS) for software-defined radio application. The frequency synthesiser has two modes: the regular mode with low phase noise performance and the low-power mode for the low-power applications at lower frequency band. The authors also propose adjustable replica (AR) bias circuit for the frequency selection multiplexer (FSMUX) in the divide-by-two divider chain to optimise the power consumption at different frequencies while keep the output s… Show more

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Cited by 2 publications
(2 citation statements)
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“…The retiming DFF is also power hungry if the VCO frequency is high. So, it can operate at the frequency of the prescaler output instead of the VCO frequency to save power [37] , as shown in Fig. 12(c).…”
Section: Power Reduction Techniquesmentioning
confidence: 99%
“…The retiming DFF is also power hungry if the VCO frequency is high. So, it can operate at the frequency of the prescaler output instead of the VCO frequency to save power [37] , as shown in Fig. 12(c).…”
Section: Power Reduction Techniquesmentioning
confidence: 99%
“…To accelerate the locking speed, there are three main technologies namely dynamic loop bandwidth [7][8][9][10][11][12], fractional-N frequency division [6,[13][14][15], feed-forward preset [16][17][18], and the emerging all-digital PLL (AD-PLL) [15,19]. Fractional-N technology can increase the reference frequency so that the loop bandwidth is no longer limited by the channel bandwidth and can be a larger value, and has been widely used.…”
Section: Introductionmentioning
confidence: 99%