A 1.0-ns/1.0-V Delay-Locked Loop With Racing Mode and Countered CAS Latency Controller for DRAM Interfaces

Lee, Hyun–Woo; Choi, Hoon; Shin, Beomju; Kim, Kyung-Hoon; Kim, Kyung-Whan; Kim, Jaeil; Kim, Kwang-Hyun; Jung, Jin Hwa; Kim, Jaehwan; Park, Eun‐Young; Kim, Jong-Sam; Kim, Jong-Hwan; Cho, Jin-Hee; Rye, Namgyu; Chun, Junhyun; Kim, Yunsaing; Kim, Chulwoo; Choi, Young-Jung; Chung, Byong-Tae

doi:10.1109/jssc.2012.2191027

Cited by 24 publications

(4 citation statements)

References 11 publications

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“…1 shows the proposed DLL architecture. To improve the delay line resolution up to a sub-gate-delay level, a merged dual delay line (MDDL) [4] is adopted and integrated with digitally controlled registers, as shown in Fig. 2.…”

Section: A Hybrid Architecture With Sub-gate Resolutionmentioning

confidence: 99%

A digital DLL with 4-cycle lock time and 1/4 NAND-delay accuracy

Kim

Jin

Chun

et al. 2015

2015 IEEE Asian Solid-State Circuits Conference (A-Sscc)

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This paper presents a fully digital delay locked loop (DLL) that can acquire lock in four clock cycles with a resolution of a 1/4 NAND-delay. The proposed DLL with a multi-dither-free phase detector acquires the initial lock in four clock cycles with 1/2 NAND-delay. Then, it utilizes a multi-dither-free phase detector, a region accumulator, and phase blenders, to improve the resolution to a 1/4 NAND-delay. The region accumulator which continuously steers the control registers and the phase blender, adaptively controls the tracking bandwidth depending on the amount of jitter, and effectively suppresses the dithering jitter. Fabricated in 65nm CMOS, the proposed DLL occupies 0.0432 mm 2 , and consumes 3.7 mW from a 1.2-V supply at 2 GHz.

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Section: A Hybrid Architecture With Sub-gate Resolutionmentioning

confidence: 99%

A digital DLL with 4-cycle lock time and 1/4 NAND-delay accuracy

Kim

Jin

Chun

et al. 2015

2015 IEEE Asian Solid-State Circuits Conference (A-Sscc)

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“…Delay lines are also susceptible to PVT variations, which compromises linearity. Therefore, DCDLs are typically used within a delay-locked loop (DLL) in order to control these mismatches, resulting in extra overhead [4], [5]. Moving on to the DTC, it is a single-input single-output block that typically generates delay through a comparator that detects the threshold crossing of a current charging a capacitor.…”

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A 0.5GHz 0.35mW LDO-Powered Constant-Slope Phase Interpolator With 0.22% INL

Elnaqib

Okuhara

Jang

et al. 2021

IEEE Trans. Circuits Syst. II

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Clock generators are an essential and critical building block of any communication link, whether it be wired or wireless, and they are increasingly critical given the push for lower I/O power and higher bandwidth in Systems-on-Chip (SoCs) for the Internet-of-Things (IoT). One recurrent issue with clock generators is multiple-phase generation, especially for lowpower applications; several methods of phase generation have been proposed, one of which is phase interpolation. We propose a phase interpolator (PI) that employs the concept of constant-slope operation. Consequently, a low-power highly-linear operation is coupled with the wide dynamic range (i.e. phase wrapping) capabilities of a PI. Furthermore, the PI is powered by a lowdropout regulator (LDO) supporting fast transient operation. Implemented in 65-nm CMOS technology, it consumes 350µW at a 1.2-V supply and a 0.5-GHz clock; it achieves energy efficiency 4×-15× lower than state-of-the-art (SoA) digital-totime converters (DTCs) and an integral non-linearity (INL) of 2.5×-3.1× better than SoA PIs, striking a good balance between linearity and energy efficiency.

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“…Moreover, the DLL also provides better jitter performance considering that there is no jitter accumulation in a voltage controlled delay line (VCDL) or digitally controlled delay line (DCDL). The application of DLL is not only limited to the clock synchronous but it is also useful for Double-Data-Rate Three (DDR3) SDRAM [1][2][3][4]. The advantages of an all-analog DLL are low jitter output and higher delay resolution.…”

Section: Introductionmentioning

confidence: 99%

A low-power, area-efficient all-digital delay-locked loop for DDR3 SDRAM controller

Chen

Wang

et al. 2014

Sci. China Inf. Sci.

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A new low-power, area efficiency all-digital delay-locked loop (ADDLL) circuit is proposed for DDR3 application. The ADDLL can process the input clock frequency ranging from 333 MHz to 800 MHz (DDR3-667/800/1066/1600) by using Phase Detector (PD), Delay Control Delay Line (DCDL), Digital Loop Filter Controller (DLFC) and Delay Generator (DG). To achieve 1.6 Gb/s/pin operation, a novel DCDL scheme is employed. The DCDL has a small delay with a shunt capacitor based digitally controlled delay element. A splitcontrol thermometer-code generator generates the control voltages used to set a current in the current-starved inverters. The testchip fabricated with a 40-nm CMOS process gives the ADDLL data rate of 667 Mbps-1.6 Gbps. Experimental results that show the power consumption is 1.87 mW at 1.1 V with active area is 0.0137 mm 2 . Keywords all-digital delay-locked loop, double-data-rate, digitally controlled delay line, shunt capacitor, thermometer code CitationChen H M, Ma S, Wang L, et al. A low-power, area-efficient all-digital delay-locked loop for DDR3 SDRAM controller.

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A 1.0-ns/1.0-V Delay-Locked Loop With Racing Mode and Countered CAS Latency Controller for DRAM Interfaces

Cited by 24 publications

References 11 publications

A digital DLL with 4-cycle lock time and 1/4 NAND-delay accuracy

A digital DLL with 4-cycle lock time and 1/4 NAND-delay accuracy

A 0.5GHz 0.35mW LDO-Powered Constant-Slope Phase Interpolator With 0.22% INL

A low-power, area-efficient all-digital delay-locked loop for DDR3 SDRAM controller

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