A digital DLL with 4-cycle lock time and 1/4 NAND-delay accuracy

Abstract

This paper presents a fully digital delay locked loop (DLL) that can acquire lock in four clock cycles with a resolution of a 1/4 NAND-delay. The proposed DLL with a multi-dither-free phase detector acquires the initial lock in four clock cycles with 1/2 NAND-delay. Then, it utilizes a multi-dither-free phase detector, a region accumulator, and phase blenders, to improve the resolution to a 1/4 NAND-delay. The region accumulator which continuously steers the control registers and the phase blender, adaptively controls the tracking bandwidth depending on the amount of jitter, and effectively suppresses the dithering jitter. Fabricated in 65nm CMOS, the proposed DLL occupies 0.0432 mm 2 , and consumes 3.7 mW from a 1.2-V supply at 2 GHz.

A Design of a Dual Delay Line DLL with Wide Input Duty Cycle Range

“…In the feedback DLL, when the DLL is locked, the rising edge of the DLL output clock needs to be aligned with the rising edge of the external clock, i.e., the external clock is delayed by an integer number of Tck after RCV, DCDL, and Buffer. At this time, the delay time of each part of the system needs to satisfy Equation (1).…”

“…In dynamic random-access memory (DRAM), dual in-line memory modules (DIMMs) are still used for low cost and high memory capacity. To solve the clock skew problem associated with the on-chip clock distribution network and the use of DIMMs in the memory bus, DLL [1][2][3] and phase-locked loop (PLL) [4][5][6][7] are used to generate clock signals in phase with the external input clock, synchronizing internal data transfer in DRAM with the external controller clock [8]. DLLs are an important part of modern DRAM technology because they enable high-speed data transfer rates while ensuring data accuracy and reliability.…”