A 0.9ns random cycle 36Mb network SRAM with 33mW standby power

Pilo, H.; Braceras, G.; Hall, Shawn A.; Lamphier, S.; Miller, M.; Roberts, A.; Wistort, Reid

doi:10.1109/vlsic.2004.1346589

Cited by 7 publications

(2 citation statements)

References 2 publications

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“…SAE is raised high) and the wordlines are deactivated (and pre-charging of the bit-lines starts) is very small [14]. As soon as the bit-lines are pre-charged to back to V DD the Vgs of the P L-R reduces to "0" which turns "off" the transistor P L-R .…”

Section: Design Considerationsmentioning

confidence: 99%

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Leakage Current Based Stabilization Scheme for Robust Sense-Amplifier Design for Yield Enhancement in Nano-scale SRAM

Mukhopadhyay

Raychowdhury

Mahmoodi

et al. 2005

14th Asian Test Symposium (ATS'05)

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In this paper, we develop a method to analyze the probability of access failure in SRAM array (due to random Vt variation in transistors) by jointly considering variations in cell and senseamplifiers. Our analysis shows that, improving robustness of senseamplifier is extremely important for reducing memory access failure probability and improving yield. We present a process variation tolerant sense amplifier suitable for SRAM array designed in sub100nm CMOS technologies. The proposed technique reduces the failure probability of sense amplifiers by more than 80% with negligible penalty in the sensing delay.

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Section: Design Considerationsmentioning

confidence: 99%

“…Fig. 14b also shows that, for a target tolerable value of the failure probability, the stabilization scheme allows an early firing of senseamp enable signal, which helps to reduce memory access time [4][5][6][7][8][9][10][11][12][13][14][15].…”

Section: Sensitivity To Temperature and Bit-differentialmentioning

confidence: 99%