14th Asian Test Symposium (ATS'05) 2005
DOI: 10.1109/ats.2005.73
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Leakage Current Based Stabilization Scheme for Robust Sense-Amplifier Design for Yield Enhancement in Nano-scale SRAM

Abstract: In this paper, we develop a method to analyze the probability of access failure in SRAM array (due to random Vt variation in transistors) by jointly considering variations in cell and senseamplifiers. Our analysis shows that, improving robustness of senseamplifier is extremely important for reducing memory access failure probability and improving yield. We present a process variation tolerant sense amplifier suitable for SRAM array designed in sub100nm CMOS technologies. The proposed technique reduces the fail… Show more

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Cited by 5 publications
(4 citation statements)
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“…7(b) shows the tied-gate and Independently-controlled-Gate (IG) configurations [15][16]. Several literatures have demonstrated the benefit of using independently-controlled-gate devices [10][11][12]. Our analyses are based on FinFET device with N a = 1×10 17 cm -3 , L eff = 25nm, W fin = 7nm, H fin = 20nm and EOT = 0.65nm, consistent with the ITRS Roadmap projection.…”
Section: Clsas Using Finfet Devicesmentioning
confidence: 53%
See 1 more Smart Citation
“…7(b) shows the tied-gate and Independently-controlled-Gate (IG) configurations [15][16]. Several literatures have demonstrated the benefit of using independently-controlled-gate devices [10][11][12]. Our analyses are based on FinFET device with N a = 1×10 17 cm -3 , L eff = 25nm, W fin = 7nm, H fin = 20nm and EOT = 0.65nm, consistent with the ITRS Roadmap projection.…”
Section: Clsas Using Finfet Devicesmentioning
confidence: 53%
“…These variations severely impact the robustness of nanoscale SRAMs [9]. Several offset compensation techniques for SA have been proposed [10][11][12]. However, most of them suffer from costly trade-off such as escalating complexities and overly extended areas, which may not be as cost-effective as directly increasing the device size for yield improvement.…”
Section: Introductionmentioning
confidence: 99%
“…As discussed earlier, process variation may cause a 1) wrong read after the sense amplifier is enabled or 2) or violation of sensing time constraint [5]. There can be multiple causes for parametric failure of memory access but in all cases they can be mapped into offset voltage ΔV in [1].…”
Section: Impact Of Process Variationsmentioning
confidence: 99%
“…voltage mode and current mode [1][3][4] [5]. In the voltage mode, the circuits amplify a small differential voltage in the bit lines to a full swing output whereas in the current mode, it amplifies the small differential current.…”
Section: Introductionmentioning
confidence: 99%