Variation tolerant CLSAs for nanoscale Bulk-CMOS and FinFET SRAM

Abstract

In this paper, we propose three Current-Latch-based Sense Amplifiers (CLSA) configurations for nanoscale Bulk-CMOS SRAM and several CLSAs using FinFET devices with independently-controlled-gate. Extensive simulations suggest the proposed structures are robust against random offset errors. The proposed CLSA structures feature significant offset suppression capabilities with σ offset reduction up to 74% (76%) in 40nm Bulk-CMOS (25nm FinFET-SOI) technology compared with the conventional CLSA. Meanwhile, up to 27% (52%) shorter sensing delay, 71% (77%) shorter Time-To-Sense and 73% (76%) lower bit-line power consumption are achieved in 40nm Bulk-CMOS (25nm FinFET-SOI). Finally, the proposed CLSA structures significantly enhance the sensing yield and affordable number of cells per bit-line, thus improving the array efficiency hence overall area and performance/power as well.

Design of High-Speed, Low-Power Sensing Circuits for Nano-Scale Embedded Memory

“…Some previously proposed SAs combine the features of VLSAs and CLSAs to reduce the V OS , which can be referred to as hybrid latch-type SAs (HYSA) [ 28 , 29 , 30 , 31 , 32 , 33 ]. Figure 7 a shows one example of an HYSA proposed in [ 32 ], the variation-tolerant SA (VTSA).…”

“…However, this approach incurs area and power overhead. To reduce the V OS while minimizing the area and power overhead, various offset reducing circuit techniques have been proposed [ 22 , 23 , 24 , 25 , 26 , 27 , 28 , 29 , 30 , 31 , 32 , 33 , 34 , 35 , 36 , 37 , 38 , 39 , 40 , 41 , 42 , 43 , 44 , 45 , 46 , 47 ]. This paper aims to conduct a comparative analysis of these circuits, explaining their effectiveness in reducing the V OS and achieving power and performance benefits.…”