A 0.9-$\mu$A Quiescent Current Output-Capacitorless LDO Regulator With Adaptive Power Transistors in 65-nm CMOS

Chong, Sau Siong; Chan, P.K.

doi:10.1109/tcsi.2012.2215392

Cited by 124 publications

(83 citation statements)

References 22 publications

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“…According to (11) and (13), a larger R FB improves the SR G as well as regulating accuracy. However, this pushes the complex poles p 2;3 to a lower frequency as proved in (16), degrading the PM throughout the allowable range of load current, thus the circuit may lead to instability.…”

Section: Post-layout Simulation Resultsmentioning

confidence: 99%

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A low-power fast transient output capacitor-free adaptively biased LDO based on slew rate enhancement for SoC applications

Lim

Lai

Tan

et al. 2015

Microelectronics Journal

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Section: Post-layout Simulation Resultsmentioning

confidence: 99%

“…For portable handheld devices, efficiency is a critical key in extending the battery life [10][11][12]. This can be achieved by lowering down the quiescent current ðI Q Þ and dropout voltage ðV DO Þ.…”

Section: Introductionmentioning

confidence: 99%

A low-power fast transient output capacitor-free adaptively biased LDO based on slew rate enhancement for SoC applications

Lim

Lai

Tan

et al. 2015

Microelectronics Journal

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“…Some papers in connection with output-capacitorless LDOs have been reported in recent years [6][7][8][9][10][11][12][13][14]. The reported LDO in [6] uses a capacitor multiplier stage to improve the dynamic performance of the LDO, at the expense of increasing its power consumption.…”

Section: Introductionmentioning

confidence: 99%

“…Additionally, the stability of the regulator goes down significantly for output load current less than 50 μA. The proposed regulator in [13] can switch between two and three stages with respective power transistor, depending on the load demands. Indeed, the main core of the LDO consists of two stages, an error amplifier and a pass transistor.…”

Section: Introductionmentioning

confidence: 99%

Output‐capacitorless segmented low‐dropout voltage regulator with controlled pass transistors

Saberkari

Qaraqanabadi

Shirmohammadli

et al. 2015

Circuit Theory & Apps

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SUMMARYThis article presents a low quiescent current output-capacitorless quasi-digital complementary metal-oxidesemiconductor (CMOS) low-dropout (LDO) voltage regulator with controlled pass transistors according to load demands. The pass transistor of the LDO is segmented into two smaller sizes based on a proposed segmentation criterion, which considers the maximum output voltage transient variations due to the load transient to different load current steps to find the suitable current boundary for segmentation. This criterion shows that low load conditions will cause more output variations and settling time if the pass transistor is used in its maximum size. Furthermore, this situation is the worst case for stability requirements of the LDO. Therefore, using one smaller transistor for low load currents and another one larger for higher currents, a proper trade-off between output variations, complexity, and power dissipation is achieved. The proposed LDO regulator has been designed and post-simulated in HSPICE in a 0.18 μm CMOS process to supply a stable load current between 0 and 100 mA with a 40 pF on-chip output capacitor, while consuming 4.8 μA quiescent current. The dropout voltage of the LDO is set to 200 mV for 1.8 V input voltage. The results reveal an improvement of approximately 53% and 25% on the output voltage variations and settling time, respectively.

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“…Other dynamic biasing method is based on high-pass filter (HPF) with capacitive coupling. It can be utilized to increase bias current of error amplifier momentarily [13][14][15][16][17][18][19][20][21]. Another option is to construct a current-boosting voltage buffer or a differentiator, aiming for bandwidth and slew-rate improvement [22,23].…”

Section: Introductionmentioning

confidence: 99%

A capacitor-less LDO regulator with dynamic transconductance enhancement technique

Ming

Zhang

Yang

et al. 2015

Analog Integr Circ Sig Process

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A current-efficient, capacitor-less low-dropout regulator (LDO) with fast-transient response for portable applications is presented in this paper. It makes use of an adaptively biased common-gate amplifier to extend loop bandwidth of the LDO at heavy loads. Moreover, a dynamic transconductance enhancement circuit based on capacitive coupling detects rapid voltage spikes at the output, providing an extra large current to charge or discharge the gate capacitance of power transistor momentarily during transient. The proposed circuit has been implemented in a 0.35 lm standard CMOS process. Experimental results show that this fully-integrated LDO can deliver 100 mA load current at 200 mV dropout voltage. It only consumes 15 lA quiescent current and is able to recover within 1 ls under the maximum load current change, with undershoot/overshoot voltages controlled below 250 mV. Loop stability is kept well at light loads (I load = 100 lA) even when a 100 pF output-parasitic capacitor is applied.

show abstract

A 0.9-$\mu$A Quiescent Current Output-Capacitorless LDO Regulator With Adaptive Power Transistors in 65-nm CMOS

Cited by 124 publications

References 22 publications

A low-power fast transient output capacitor-free adaptively biased LDO based on slew rate enhancement for SoC applications

A low-power fast transient output capacitor-free adaptively biased LDO based on slew rate enhancement for SoC applications

Output‐capacitorless segmented low‐dropout voltage regulator with controlled pass transistors

A capacitor-less LDO regulator with dynamic transconductance enhancement technique

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