A 0.6-V, 74.2-dB DR Continuous-Time Sigma–Delta Modulator With Inverter-Based Amplifiers

Aguirre, Paulo César C. de; Susin, Altamiro

doi:10.1109/tcsii.2018.2853088

Cited by 15 publications

(7 citation statements)

References 16 publications

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“…Current CT-SDM designs for low-voltage applications adopt inverter-based OTAs due to their hightransconductance efficiency [2], [20], [24], [25], [26]. However, process and mismatch variations can highly affect the performance of inverter-based OTAs, thus the use of com- pensation techniques are mandatory.…”

Section: A First Otamentioning

confidence: 99%

“…The first stage OTA also adopts a bulk-bias approach in the NMOS transistors. A current source and a bulk-based current mirror generate the bias voltage of the first stage NMOS transistor using a replica inverter in a diode connection fashion, as introduced in [24]. It helps to mitigate the first stage DC gain and GBW variation across process corners and mismatch since a reference current is adopted to adjust the bias point.…”

Section: A First Otamentioning

confidence: 99%

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Behavioral and Electrical Modeling of a 0.5-V Third-Order Continuous-Time Sigma-Delta Modulator with FIR DAC for Audio Applications

Cortez

Girardi

Severo

et al. 2023

JICS

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Most mobile and wearable devices present digital audio signal processing capabilities. Since the nature of audio signals is analog, there is a need to use analog-to-digital converters (ADCs) with high-resolution for a high signal-to-noise ratio audio acquisition. This paper presents the high-level modeling and design of a continuous-time third-order sigma-delta modulator (CT-SDM) with an FIR DAC for audio devices, using a supply voltage of 0.5 V. The design is divided in three steps and is carried out using the Delta-sigma toolbox and a discrete-time to continuous-time (DT-CT) transformation. First, the schematic implementation with verilogA models is done to estimate the first-integrator amplifier specifications for the modulator to provide 14 bits of ENOB. Following, a two-stage inverter-based amplifier is designed and used to verify the design strategy. Finally, a transistor-level implementation of OTAs and comparator is done to evaluate the CT-SDM performance. An in-depth analysis and discussion are presented to explain the achieved results with those transistor-level circuits.

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Section: A First Otamentioning

confidence: 99%

Section: A First Otamentioning

confidence: 99%

Behavioral and Electrical Modeling of a 0.5-V Third-Order Continuous-Time Sigma-Delta Modulator with FIR DAC for Audio Applications

Cortez

Girardi

Severo

et al. 2023

JICS

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“…New topologies have been proposed compensating the ELD and the aforementioned inconveniences with more stages in the OTA [7]. Another recent option is the single-amplifier resonator in CT modulators [8], [9]. The properties in this CT circuit improve the overall modulator's resolution at the expense of more passive elements.…”

Section: Introductionmentioning

confidence: 99%

A 65nm Continuous-Time Sigma-Delta Modulator With Limited OTA DC Gain Compensation

González-Díaz

Pareschi

2020

IEEE Access

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This paper explores the effects of compensating the performance degradation in high-speed Continuous-Time Sigma-Delta modulators when the loop integrators are implemented through limited gain Operational Transconductance Amplifiers. Yet, the low DC-gain strongly affects both integrator magnitude and phase responses, with a reduction in the overall effective number of bits. This work models the degradation as due to a signal-dependent memory-less perturbation and theoretically studies its compensation by feeding an opposite signal back to the integrator input. The implementation and experimental results on a 65nm CMOS 2nd order prototype evaluate the performance increase with this technique, where no other compensation, nor any digital calibration, is included. Tested in different conditions, the compensated prototype improves more than 1.5 bit the ENoB with respect to the uncompensated counterpart. For a sampling frequency of 500 MHz the power consumption is 1.7mW, resulting in a 477.2fJ/conv-lev Walden and a 148.8dB Schreirer Figures of Merit.

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“…Ismail and Mostafa [5] proposed a low-voltage CT-SDM with inverter-based OTAs with PVT compensation performed by changing the current drawn for each of the inverter transistors. In [6], a 0.6 V CT-SDM with single-stage inverter-based OTAs is presented and the operating point of the inverters is controlled by a CMFB loop that changes the bulk voltage shared by PMOS and NMOS transistors.…”

mentioning

confidence: 99%

“…The variation of amplifiers UGBW across supply voltage and temperature variations can significantly reduce the modulator signal-to-noise and distortion ratio (SNDR) as stated in [7]. However, no mitigation strategy to reduce UGBW variations is addressed in [4][5][6]. In [2], the reduction of UGBW variation is accomplished by changing the inverters supply voltage at the cost of a voltage regulator while in [3] the proposed bulk bias technique provides a reduction of the cascode inverter UGBW from 54 to 11% for the slow process corner at typical power supply.…”

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confidence: 99%

PVT compensated inverter‐based OTA for low‐voltage CT sigma‐delta modulators

Aguirre

Susin

2018

Electron. lett.

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An inverter-based operational transconductance amplifier (OTA) robust to process, voltage and temperature (PVT) variations is proposed in this Letter to enable the design of low-voltage power-efficient continuous-time sigma-delta modulators (CT-SDMs). The proposed OTA significantly reduces the unity gain-bandwidth variation across PVT corners while presenting a DC gain of 41.9 dB at nominal conditions when operated at 0.6 V. The effectiveness of the proposed circuit was verified in a 180 nm CMOS process by transistor-level simulations including PVT variations and mismatch. Also, a 0.6 V third-order CT-SDM is designed to verify the robustness against voltage and temperature variations.

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A 0.6-V, 74.2-dB DR Continuous-Time Sigma–Delta Modulator With Inverter-Based Amplifiers

Cited by 15 publications

References 16 publications

Behavioral and Electrical Modeling of a 0.5-V Third-Order Continuous-Time Sigma-Delta Modulator with FIR DAC for Audio Applications

Behavioral and Electrical Modeling of a 0.5-V Third-Order Continuous-Time Sigma-Delta Modulator with FIR DAC for Audio Applications

A 65nm Continuous-Time Sigma-Delta Modulator With Limited OTA DC Gain Compensation

PVT compensated inverter‐based OTA for low‐voltage CT sigma‐delta modulators

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