A 0.6-V 1.6-mW transformer-based 2.5-GHz downconversion mixer with +5.4-dB gain and -2.8-dBm IIP3 in 0.13-/spl mu/m CMOS

Hermann, C.; Tiebout, M.; Klär, H.

doi:10.1109/tmtt.2004.840762

Cited by 57 publications

(29 citation statements)

References 10 publications

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“…2. To reduce the supply voltage (V CC ) for a mixer circuit to less than 2 V, separating the DC stacking connection between transistors is effective [10][11][12]. Unlike an Rx mixer, LO signal, which is inputted to LOIN, must be transmitted through the transformer because the transformer coupling effect becomes larger as the input frequency becomes higher when in the same conditions as the transformer.…”

Section: Transmitter Mixer Circuitmentioning

confidence: 99%

Low-power K-band pseudo-stacked mixer with linearity enhancement technique

Shiramizu

Masuda

Nakamura

et al. 2009

2009 IEEE Bipolar/BiCMOS Circuits and Technology Meeting

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A low-power transmitter mixer and a receiver mixer operating in the K-band frequency region have been developed. Both mixers can be operated at a low supply voltage of 1.5 V because of a pseudo-stacked configuration using an on-chip transformer. For the transmitter mixer, an emitter degeneration resistor in parallel with a capacitor is introduced to obtain both high linearity and high-gain. Moreover, an emitter degeneration inductor of the receiver mixer improves the linearity characteristics. The proposed mixers are fabricated using 0.18-m SiGe BiCMOS technology. The transmitter mixer achieves a conversion gain of -0.1 dB, input P1dB of -11 dBm, and IIP3 of -1.2 dBm. The receiver mixer achieves a conversion gain of 11.2 dB, input P1dB of -23 dBm, and IIP3 of -13 dBm. These results indicate that these mixer design techniques are suitable to be applied for low-power transceivers within the quasi-millimeter-wave frequency region.Index Terms -Mixer, low voltage, low power, high linearity, quasi-millimeter-wave, on-chip transformer.

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Section: Transmitter Mixer Circuitmentioning

confidence: 99%

Low-power K-band pseudo-stacked mixer with linearity enhancement technique

Shiramizu

Masuda

Nakamura

et al. 2009

2009 IEEE Bipolar/BiCMOS Circuits and Technology Meeting

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“…For an turns inductor, assume the lengths of each half turn are denoted as , the metal width is , metal thickness is , and the total length of the metal wire is Define , the voltage profile of the inductor under a single ended stimulus can be described as (2) Based on the above assumptions, the voltage of the th half turn of the inductor can be approximated as (3) Fig. 4 displays the cross-sectional view of a planar inductor and its voltage profile.…”

Section: -D Inductormentioning

confidence: 99%

“…Monolithic passive components, including inductors, transformers, and baluns, have been widely used in RF ICs design, such as low noise amplifier [1], mixer [2], and oscillators [3], etc. These components play a key role in the circuit integration, and in general have significant impacts on the overall system performance.…”

mentioning

confidence: 99%

Three-Dimensional Fully Symmetric Inductors, Transformer, and Balun in CMOS Technology

Chen

Hsu

2007

IEEE Trans. Circuits Syst. I

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Abstract-This paper presents novel three-dimensional (3-D) symmetric passive components, including inductors, transformers, and balun. Layout areas of these components are drastically reduced by 32% to 70%, while the symmetry of the input and the output ports is still maintained. The inductance mismatch in the 3-D transformer is less than 0.1%, and the coupling coefficient can be up to 0.77. The 3-D balun manifests less than 0.6-dB gain mismatch for 10-GHz range, and the phase error is less than 7 from 1-to 10-GHz frequency range according to measurement results. Furthermore, the self-resonant frequency ( SR ) of the proposed architecture is improved by 32% to 61% in contrast to their planar counterparts. On the other hand, the quality factor is degraded by less than 2 for the sake of using lower metal layers. The distributed capacitance model is utilized to validate their superiorities in SR . All the devices are fabricated in a generic 0.18-m CMOS process.

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“…The goal of this work is to develop a true ULV DR modulator for analog-digital conversion in wireless receivers which requires a 40-100 times large signal bandwidth than the existing ULV modulators, while maintaining good SNDR and power efficiency. Given that several RF front-ends at ULV have been demonstrated [23][24][25][26][27][28], this ULV DR modulator can enable the realization of fully integrated, highly digital ULV wireless receivers [25,30].…”

Section: Introductionmentioning

confidence: 99%

A 0.5 V 65.7 dB 1 MHz continuous-time complex delta sigma modulator

Pun

Tang

et al. 2010

Analog Integr Circ Sig Process

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This manuscript reports a 0.5 V 1-MHz signal bandwidth third-order continuous-time complex DR modulator for analog-to-digital conversion in GFSK receivers. A special common-mode level arrangement and gate-input self-biased amplifiers allows the modulator to meet the speed requirement at the low supply voltage. Realized in a 0.13-lm triple-well CMOS process and using only standard V T devices, the modulator achieves a peak SNDR of 61.9 dB, a dynamic range of 65.7 dB and an image rejection ratio of 46.3 dB with 3.4-mW consumption at the nominal supply of 0.5 V, and occupies a die area of 0.9 mm 2 .

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A 0.6-V 1.6-mW transformer-based 2.5-GHz downconversion mixer with +5.4-dB gain and -2.8-dBm IIP3 in 0.13-/spl mu/m CMOS

Cited by 57 publications

References 10 publications

Low-power K-band pseudo-stacked mixer with linearity enhancement technique

Low-power K-band pseudo-stacked mixer with linearity enhancement technique

Three-Dimensional Fully Symmetric Inductors, Transformer, and Balun in CMOS Technology

A 0.5 V 65.7 dB 1 MHz continuous-time complex delta sigma modulator

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