A 0.5 V 65.7 dB 1 MHz continuous-time complex delta sigma modulator

Abstract

This manuscript reports a 0.5 V 1-MHz signal bandwidth third-order continuous-time complex DR modulator for analog-to-digital conversion in GFSK receivers. A special common-mode level arrangement and gate-input self-biased amplifiers allows the modulator to meet the speed requirement at the low supply voltage. Realized in a 0.13-lm triple-well CMOS process and using only standard V T devices, the modulator achieves a peak SNDR of 61.9 dB, a dynamic range of 65.7 dB and an image rejection ratio of 46.3 dB with 3.4-mW consumption at the nominal supply of 0.5 V, and occupies a die area of 0.9 mm 2 .