A 0.5 V bulk‐driven voltage follower/DC level shifter and its application in class AB output stage

Self Cite

A family of bulk-driven CMOS operational transconductance amplifiers (OTAs) has been designed for extremely low supply voltages (0.3-0.5 V). Three OTA design schemes with different gain boosting techniques and class AB input/output stages are discussed. A detailed comparison among these schemes has been presented in terms of performance characteristics such as voltage gain, gain-bandwidth product, slew rate, circuit sensitivity to process/mismatch variations, and silicon area. The design procedures for all the compared structures have been developed. The OTAs have been fabricated in a standard 0.18-μm n-well CMOS process from TSMC. Chip test results are in good agreement with theoretical predictions and simulations.

Section: Introductionsupporting

confidence: 80%

Section: Introductionsupporting

confidence: 80%

Design and implementation of sub 0.5‐V OTAs in 0.18‐μm CMOS

Kulej

Khateb

2018

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“…In OFF state BC FET using body conventional bias BC FET using body self-adapting bias FIGURE 11 Simulation contrast of AC current of the stacked field-effect transistors (FETs) in shunt arm with conventional and new body bias techniques when P in = 36 dBm in the OFF state resistors for the body, which increases 36 wiring (4 × 8 + 2 × 2) between level shifters 19 and switch core circuitry. Without utilizing the extra voltage supply for the body (the dash line in Figure 12), the switch with the presented body strategy only stands half the amount of the contacts, which helps to simplify the complex control and wiring, as well as achieve smaller chip size.…”

Section: Num Of Stacked-fetsmentioning

confidence: 99%

“…17,18 As there exists 2 shared series arms and 8 series-shunt branches for 8 RF ports, 10 level shifters are required. The main issue with the conventional bias method is the additional wiring and contacts on and outside the FETs, as well as the need of biasing resistors for the body, which increases 36 wiring (4 × 8 + 2 × 2) between level shifters 19 and switch core circuitry. Without utilizing the extra voltage supply for the body (the dash line in Figure 12), the switch with the presented body strategy only stands half the amount of the contacts, which helps to simplify the complex control and wiring, as well as achieve smaller chip size.…”

Section: Die Area Rewardmentioning

confidence: 99%

A 0.1 to 2.7‐GHz SOI SP8T antenna switch adopting body self‐adapting bias technique for low‐loss high‐power applications

Zhang

et al. 2018

A low-loss high-power single-pole 8-throw antenna switch adopting body self-adapting bias technique in a 0.18-μm thick-film partially depleted silicon-on-insulator complementary metal-oxide-semiconductor process is implemented for multimode multiband cellular applications. A topology with symmetric port design is developed. We employ the body-contacted field-effect transistor to handle high power level and obtain low harmonic distortion. However, the conventional bias method for body-contacted field-effect transistor leads to poor insertion loss (IL), serious imbalanced voltage division, and large die size. Therefore, a new body self-adapting bias scheme is adopted to improve the IL and power handling capability with die area reward by removing the employment of extra biasing resistor and voltage supply at the body. The presented silicon-on-insulator antenna switch utilizing the new body bias strategy reveals similar harmonic performance as a conventional switch version, thanks to the analogous DC bias to the gate and body, while it exhibits effectively lower IL, imbalanced voltage division, and die area. The measured IL and 0.1-dB compression point (P −0.1dB ), at 1.9/2.7 GHz, are roughly 0.52/0.82 dB and 39.2/36.9 dBm, respectively. The overall IL and P −0.1dB are apparently improved by approximately 0.05 to 0.13 dB and 0.5 to 0.8 dBm compared with the conventional version.

“…The overall performance of the PGA could be further improved employing a class AB VOA. Appropriate ULV class AB gain stage has been presented in [29]. With the second digital word applied to OTA I , the voltage gain could be regulated from À18 dB to 18 dB.…”

Section: Comparison With Other Designsmentioning

confidence: 99%

0.3‐V bulk‐driven programmable gain amplifier in 0.18‐µm CMOS

Kulej

Khateb

2016

Self Cite

A new solution for an ultra low voltage bulk-driven programmable gain amplifier (PGA) is described in the paper. While implemented in a standard n-well 0.18-μm complementary metal-oxide-semiconductor (CMOS) process, the circuit operates from 0.3 V supply, and its voltage gain can be regulated from 0 to 18 dB with 6-dB steps. At minimum gain, the PGA offers nearly rail-to-rail input/output swing and the input referred thermal noise of 2.37 μV/Hz 1/2 , which results in a 63-dB dynamic range (DR). Besides, the total power consumption is 96 nW, the signal bandwidth is 2.95 kHz at 5-pF load capacitance and the thirdorder input intercept point (IIP 3 ) is 1.62 V. The circuit performance was simulated with LTspice. Copyright