A 0.3 V Rail-to-Rail Ultra-Low-Power OTA with Improved Bandwidth and Slew Rate

Centurelli, Francesco; Sala, R.; Monsurrò, Pietro; Scotti, Giuseppe; Trifiletti, Alessandro

doi:10.3390/jlpea11020019

Cited by 22 publications

(16 citation statements)

References 45 publications

(59 reference statements)

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“…However, since most works presented in the literature show an asymmetric slew-rate, it is more meaningful to consider the worst case slew-rate. Consequently, as in [40], we define the FOM L WC as:…”

Section: Discussion and Comparison With The Literaturementioning

confidence: 99%

“…The topology of the blocks denoted as stage 1 in Figure 1 is reported in Figure 2, and is made up of transistors M 1A , M 1B and M 2A , M 2B . This input stage has the same topology adopted for the OTA in [40]. It is a bulk-driven stage in which the bias current is accurately set through the V GN voltage applied to the gate of transistor M 2A .…”

Section: Stagementioning

confidence: 99%

“…The bulk-driven technique [29][30][31] allows rail-to-rail ICMR in ULV amplifiers at the cost of reduced gain and a resistive input impedance component. Bulk-driven amplifiers are surely one of the best alternatives to attain rail-to-rail input-output swing when a well-defined bias or common mode current is required to increase the robustness against process, supply voltage, and temperature (PVT) variations [32][33][34][35][36][37][38][39][40][41][42]. Indeed, the signal-free gate terminals can be used to accurately set the bias current of the different OTA stages.…”

Section: Introductionmentioning

confidence: 99%

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A Tree-Based Architecture for High-Performance Ultra-Low-Voltage Amplifiers

Centurelli

Sala

Monsurrò

et al. 2022

JLPEA

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In this paper, we introduce a novel tree-based architecture which allows the implementation of Ultra-Low-Voltage (ULV) amplifiers. The architecture exploits a body-driven input stage to guarantee a rail-to-rail input common mode range and body-diode loading to avoid Miller compensation, thanks to the absence of high-impedance internal nodes. The tree-based structure improves the CMRR of the proposed amplifier with respect to the conventional OTA architectures and allows achievement of a reasonable CMRR even at supply voltages as low as 0.3 V and without tail current generators which cannot be used in ULV circuits. The bias currents and the static output voltages of all the stages implementing the architecture are accurately set through the gate terminals of biasing transistors in order to guarantee good robustness against PVT variations. The proposed architecture and the implementing stages are investigated from an analytical point of view and design equations for the main performance metrics are presented to provide insight into circuit behavior. A 0.3 V supply voltage, subthreshold, ultra-low-power (ULP) OTA, based on the proposed tree-based architecture, was designed in a commercial 130 nm CMOS process. Simulation results show a dc gain higher than 52 dB with a gain-bandwidth product of about 35 kHz and reasonable values of CMRR and PSRR, even at such low supply voltages and considering mismatches. The power consumption is as low as 21.89 nW and state-of-the-art small-signal and large-signal FoMs are achieved. Extensive parametric and Monte Carlo simulations show the robustness of the proposed circuit to PVT variations and mismatch. These results confirm that the proposed OTA is a good candidate to implement ULV, ULP, high performance analog building blocks for directly harvested IoT nodes.

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Section: Discussion and Comparison With The Literaturementioning

confidence: 99%

Section: Stagementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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A Tree-Based Architecture for High-Performance Ultra-Low-Voltage Amplifiers

Centurelli

Sala

Monsurrò

et al. 2022

JLPEA

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“…Thus, body-driven (BD) OTAs have become more popular over the years. Indeed, BD amplifiers employ the bulk as an input terminal to achieve rail-to-rail input common-mode range (ICMR) and at the same time a well-defined bias point, thanks to gate biasing [27][28][29][30][31][32][33][34]. However, BD-OTAs aren't suitable for switching applications, due to their input impedance.…”

Section: Introductionmentioning

confidence: 99%

A Novel OTA Architecture Exploiting Current Gain Stages to Boost Bandwidth and Slew-Rate

et al. 2021

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A novel architecture and design approach which make it possible to boost the bandwidth and slew-rate performance of operational transconductance amplifiers (OTAs) are proposed and employed to design a low-power OTA with top-of-class small-signal and large-signal figures of merit (FOMs). The proposed approach makes it possible to enhance the gain, bandwidth and slew-rate for a given power consumption and capacitive load, achieving more than an order of magnitude better performance than a comparable conventional folded cascode amplifier. Current mirrors with gain and a push–pull topology are exploited to achieve symmetrical sinking and sourcing output currents, and hence class-AB behavior. The resulting OTA was implemented using the 130 nm STMicroelectronics process, with a supply voltage of 1 V and a power consumption of only 1 µW. Simulations with a 200 pF load capacitance showed a gain of 92 dB, a unity-gain frequency of 141 kHz, and a peak slew-rate of 30 V/ms, with a phase margin of 80°, and good noise, PSRR and CMRR performance. The small-signal and large-signal current and power FOMs are the highest reported in the literature for comparable amplifiers. Extensive parametric and Monte Carlo simulations show that the OTA is robust against process, supply voltage and temperature (PVT) variations, as well as against mismatches.

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“…For its characteristics, it suits the sensing section, where high precision and moderate bandwidth are required. Due to the reduction in the power supply voltage, multistage topologies are often adopted in these amplifiers, and the optimization of the power consumption must face with noise, dynamic range and speed trade-offs [24][25][26][27][28][29][30][31][32][33][34][35][36]. Ultra-low-power amplifiers cut down the power consumption by biasing all the transistors in the sub-threshold region; however, the speed requirements are more arduous to fulfill also because the slew-rate effects produce serious limitations.…”

Section: Introductionmentioning

confidence: 99%

A gm/ID-Based Design Strategy for IoT and Ultra-Low-Power OTAs with Fast-Settling and Large Capacitive Loads

Giustolisi

Palumbo

2021

JLPEA

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In this paper, a new strategy for the design of ultra-low-power CMOS operational transconductance amplifiers (OTAs), using the gm/ID approach, is proposed for the Internet-of-things (IoT) scenario. The strategy optimizes the speed/dissipation of the OTA in terms of settling time, including slew-rate effects. It was designed for large capacitive loads and for transistors biased in the sub-threshold region, but it is also suitable for low-capacitive loads or for transistors biased in the saturation region. To validate the proposed strategy, a well-known three-stage OTA was designed starting from capacitive load and settling time requirements. Simulations confirmed that the OTA satisfies the specifications (even under Monte Carlo analysis), thus proving the correctness of the proposed approach.

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A 0.3 V Rail-to-Rail Ultra-Low-Power OTA with Improved Bandwidth and Slew Rate

Cited by 22 publications

References 45 publications

A Tree-Based Architecture for High-Performance Ultra-Low-Voltage Amplifiers

A Tree-Based Architecture for High-Performance Ultra-Low-Voltage Amplifiers

A Novel OTA Architecture Exploiting Current Gain Stages to Boost Bandwidth and Slew-Rate

A gm/ID-Based Design Strategy for IoT and Ultra-Low-Power OTAs with Fast-Settling and Large Capacitive Loads

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