A 0.3 pJ/bit 20 Gb/s/Wire Parallel Interface for Die-to-Die Communication

Dehlaghi, Behzad; Carusone, Anthony Chan

doi:10.1109/jssc.2016.2596773

Cited by 27 publications

(9 citation statements)

References 12 publications

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“…They used length matching of data and clock lines on the package to simplify the clock and data recovery in the receiver side. Dehlaghi et al demonstrated silicon interposer based die-to-die link for maximum 20 Gb/s data rate [19]. The signalling topology uses passive termination on the transmitter for equalization.…”

Section: Die_0mentioning

confidence: 99%

Holistic Die-to-Die Interface Design Methodology for 2.5-D Multichip-Module Systems

Chaudhary¹,

Heinig

Choubey

2021

IEEE Trans. Compon., Packag. Manufact. Technol.

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More than Moore technologies can be supported by system level diversification enabled by chiplet based integrated systems within multi-chip-modules (MCM) and silicon interposer based 2.5D systems. The division of large system-on-chip dies into smaller chiplets with different technology nodes specific to the chiplet application requirement enables the performance enhancement at system level while achieving lower power consumption. However, these chiplets need to communicate between each other. Routing resources in MCM and 2.5D systems are limited due to system size and thickness restrictions. This work presents energy/bit optimization approach for multi-chip systems with possibility of co-optimization with the routing resources defined by the signalling pitch. Holistic design methodologies are shown which can be further extended by the designer to define the application specific constraints. A detailed analysis of energy per bit relationship to the voltage swing requirement for different topologies is presented along with a specific CML signalling oriented design flow for 2.5D chip to chip interfaces as an example of topology specific optimization possibilities within this methodology.

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Section: Die_0mentioning

confidence: 99%

Holistic Die-to-Die Interface Design Methodology for 2.5-D Multichip-Module Systems

Chaudhary¹,

Heinig

Choubey

2021

IEEE Trans. Compon., Packag. Manufact. Technol.

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“…Table I summarizes the proposed channel performance and makes comparisons with the state-of-the-arts. Baseband based interconnect channel [21] has very high bandwidth density due to the small effective channel area, but it is not scalable to higher frequencies. The proposed work have the bandwidth density of 33.3 GHz/mm 2 and the FoM of 832 GHz/mm/dB for the mode E y11 , and the bandwidth density of 90.5 GHz/mm 2 and the FoM of 2262 GHz/mm/dB for the modes E x11 .…”

Section: B Measurementmentioning

confidence: 99%

Ortho-Mode Sub-THz Interconnect Channel for Planar Chip-to-Chip Communications

Ding

et al. 2018

IEEE Trans. Microwave Theory Techn.

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Abstract-This paper presents for the first time the design, fabrication, and demonstration of a dielectric waveguide based ortho-mode sub-THz interconnect channel for planar chip-tochip communications. By combining the proposed new transition of microstrip line to dielectric waveguide orthogonally, the orthomode transition is constructed to form an ortho-mode channel. The measured minimum insertion losses for the Ey11 mode and the Ex11 mode are 6.6 dB with 20.3 GHz 3-dB bandwidth and 6.5 dB with 55.2 GHz 3-dB bandwidth, respectively. The simulation and measurement results agree well with each other.

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“…Die-to-die I/O interfaces can be implemented as a serial link or a parallel bus to transfer massive amounts of data with low latency and error-free characteristics. A serial link-based I/O interface minimizes the number of required lanes by using a simple extra-short reach/ultra-short reach (XSR/USR) SerDes physical layer devices (PHY) with a high data rate per lane of up to 112 Gbps [19,20,21] On the other hand, the parallel bus-based I/O interface provides the required bandwidth using a huge number of ultra-fine pitch low-speed (up to 16 Gbps/line) single-ended lines [22][23][24][25][26][27].…”

Section: Introductionmentioning

confidence: 99%

“…The first, shown in Fig. 1(a), is a parallel bus die-to-die I/O interface that uses a forwarded clocking (or source synchronous clocking) scheme [22,23,26,27]. Usually, one clock lane and multiple data lanes are placed in parallel.…”

Section: Introductionmentioning

confidence: 99%

A Fast-Lock All-Digital Clock Generator for Energy Efficient Chiplet-Based Systems

Jin

Kim

2022

IEEE Access

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An all-digital clock frequency multiplier that achieves excellent locking time for an energyefficient chiplet-based system-on-chip (SoC) design is presented. The proposed architecture is based on an all-digital multiplying delay-locked loop (MDLL) to provide fast locking time and multiplied output clock frequency. The proposed MDLL has two operation modes: TDC tracking and sequential tracking. At the beginning of the operation, the MDLL utilizes a cyclic Vernier time-to-digital converter (TDC) to detect the initial phase error between the reference clock and the output clock. Then the TDC generates a digital code word (DCW) for controlling the digitally controlled oscillator (DCO) to achieve a fast lock time. The gains of TDC and DCO are designed to match well with each other, enabling phase and frequency locking in only two searches in the TDC tracking mode. After locking, the TDC is turned off, and the MDLL performs the sequential tracking mode and minimizes jitter by using the delta-sigma modulator (DSM)-based dithering jitter reduction scheme. The prototype all-digital MDLL is fabricated in a 40-nm CMOS process and achieves a fast lock time of less than six reference clock cycles at 1.6 GHz from a 100 MHz reference clock. Even when the 100 MHz reference clock has a relatively high RMS jitter of 2.19 ps (peak-to-peak jitter =15.74 ps), the measured RMS and peak-to-peak jitter values of the 1.6 GHz MDLL output clock are only 2.75 ps and 23.01 ps, respectively. The proposed all-digital MDLL occupies an active area of only 0.024 mm 2 and dissipates 3.56 mW at 1.6 GHz.INDEX TERMS MDLL, multiplying delay-locked loop, clock generator, time-to-digital converter, TDC, digitally-controlled oscillator, PLL, chiplet, die-to-die interface, heterogeneous integration, SoC, SiP.

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A 0.3 pJ/bit 20 Gb/s/Wire Parallel Interface for Die-to-Die Communication

Cited by 27 publications

References 12 publications

Holistic Die-to-Die Interface Design Methodology for 2.5-D Multichip-Module Systems

Holistic Die-to-Die Interface Design Methodology for 2.5-D Multichip-Module Systems

Ortho-Mode Sub-THz Interconnect Channel for Planar Chip-to-Chip Communications

A Fast-Lock All-Digital Clock Generator for Energy Efficient Chiplet-Based Systems

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