A 0.18 μm CMOS logic technology with dual gate oxide and low-k interconnect for high-performance and low-power applications

SRAM devices and circuits optimization toward energy efficiency in multi-V CMOS

“…SRAMs, however, require additional considerations such as array structures, active-switching, and leakage energy. Although dual-V th and multi-V th schemes have been utilized for power reduction [23,24], minimum energy-driven device selections have been rarely visited. In this section, we will analyze SRAM energy minimization considering the option of multi-V th devices.…”

“…Standby leakage reduction is also critical in enhancing energy efficiency. Bitline leakage elimination techniques [19,20], leakage reduction schemes using sleep transistors [21,22] and multi-V th devices [23,24] have been introduced.…”

A GaAs monolithic anti-series varactor pair for voltage-controlled capacitance with reduced RF nonlinearity

“…This CMOS SPDT switch is implemented by commercial standard 0.18-m MS/RF CMOS technology which provides one poly layer for the gate of the MOS and six metal layers for inter-connection [10], [11]. The substrate conductivity is approximately 10 S/m.…”

A 1.85fW/bit ultra low leakage 10T SRAM with speed compensation scheme

“…The bit-cell area ( Fig. 1) is 17.48µm 2 , 3.97× larger than a traditional 6T cell [7] but 2.3× smaller than the previous low leakage 14T SRAM [1]. Since logic design rules are used in this design, area overhead can be mitigated with pushed SRAM design rules.…”

“…A low leakage 14T SRAM cell with stacked HVT devices [1] has been previously proposed; however, its area is 9.1× larger than the traditional 6T cell [7] and the HVT devices degrades write performance by more than 10× compared to the read speed. To overcome these limitations and reduce leakage further, this work proposes a new ultra low leakage SRAM, referred to as the low leakage 10T SRAM, that exploits a boosted supply.…”