A 1.85fW/bit ultra low leakage 10T SRAM with speed compensation scheme

Kim, Dae-Yeon; Chen, Gregory; Fojtik, Matthew; Seok, Mingoo; Blaauw, David; Sylvester, Dennis

doi:10.1109/iscas.2011.5937503

Cited by 26 publications

(9 citation statements)

References 9 publications

(13 reference statements)

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“…The low power techniques utilized are ultra high threshold voltage and thick gate oxide to keep the leakage power low in the capacitance to digital converter. The SRAM is a 10T cell that uses gate length biasing in the dataretaining portion while power gating the read buffer to acheive 2.4 fW/bit standby leakage [71]. The V DD is scaled down close to the minimum energy point so the micro processor and SRAM consume only 90 nW combined at 0.45 V in active mode.…”

Section: Solar Energymentioning

confidence: 99%

Low Power Design for Future Wearable and Implantable Devices

Lundager

Zeinali

Tohidi

et al. 2016

JLPEA

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With the fast progress in miniaturization of sensors and advances in micromachinery systems, a gate has been opened to the researchers to develop extremely small wearable/implantable microsystems for different applications. However, these devices are reaching not to a physical limit but a power limit, which is a critical limit for further miniaturization to develop smaller and smarter wearable/implantable devices (WIDs), especially for multi-task continuous computing purposes. Developing smaller and smarter devices with more functionality requires larger batteries, which are currently the main power provider for such devices. However, batteries have a fixed energy density, limited lifetime and chemical side effect plus the fact that the total size of the WID is dominated by the battery size. These issues make the design very challenging or even impossible. A promising solution is to design batteryless WIDs scavenging energy from human or environment including but not limited to temperature variations through thermoelectric generator (TEG) devices, body movement through Piezoelectric devices, solar energy through miniature solar cells, radio-frequency (RF) harvesting through antenna etc. However, the energy provided by each of these harvesting mechanisms is very limited and thus cannot be used for complex tasks. Therefore, a more comprehensive solution is the use of different harvesting mechanisms on a single platform providing enough energy for more complex tasks without the need of batteries. In addition to this, complex tasks can be done by designing Integrated Circuits (ICs), as the main core and the most power consuming component of any WID, in an extremely low power mode by lowering the supply voltage utilizing low-voltage design techniques. Having the ICs operational at very low voltages, will enable designing battery-less WIDs for complex tasks, which will be discussed in details throughout this paper. In this paper, a path towards battery-less computing is drawn by looking at device circuit co-design for future system-on-chips (SoCs). dynamic power consumption, which means that a great deal of the power spent, is wasted solely on heat generation [1]. This can be dealt with by further researching cooling and packaging in order to avoid overheating the circuits; however, this is an expensive and time limited solution, so this paper addresses methods to generally reduce the overall power consumption of the systems.Since the Internet of Things (IoT) revolution, a new focus has been made on making smart phones, smart watches, tablets etc. even smaller whilst increasing the computation power. And with the recent interest in the Internet of Bio-Nano Things (IoBNT) [2], the focus has moved from just increasing the computation power to also creating extremely compact, ultra low power designs that enable small sensors and actuators to operate independently of wired data connections and external power sources. Especially for implanted sensors, the size restriction is crucial for the bio-compatibility and therefore, ...

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Section: Solar Energymentioning

confidence: 99%

Low Power Design for Future Wearable and Implantable Devices

Lundager

Zeinali

Tohidi

et al. 2016

JLPEA

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“…The robustness to terrestrial radiation being a strong requirement for targeted medical applications, it can be achieved by using error correcting codes which rely on the fact that a radiation impact does not flips more than 2 bits within a word. This governed the choice of by-8 multiplexer while the bitcells in [3] and [6] do not allow such multiplexing.…”

Section: A Sram Peripherymentioning

confidence: 99%

“…Several ULV memories have been reported in recent years to offer ULV design ability, however the bitcell reported in [3], [4] cannot be interleaved and suffer from intrinsic Radiation induced Soft Error Rate reliability weakness, further explained. The bitcell reported in [5] needs voltage footer supply modulation which adds design complexity, similarly, the design reported in [6] needs an assistance extra supply and does not withstand interleaving. Thus we believe there is a need for a ULV SRAM working around these limitations to enable industrial ULV applications with single supply and SER correction capability.…”

Section: Introductionmentioning

confidence: 99%

A 0.32V, 55fJ per bit access energy, CMOS 65nm bit-interleaved SRAM with radiation Soft Error tolerance

Clerc

Abouzeid

Gasiot

et al. 2012

2012 IEEE International Conference on IC Design &Amp; Technology

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A 32kb memory is presented with an Ultra Low Voltage optimized 10 transistors bitcell designed to withstand an extended voltage range from 1.2V down to 0.35V, achieving 1.77pJ low energy access. A validation circuit was fabricated in 65nm CMOS and exhibits wafer level yield above 95% at 0.4V, 1MHz. Packaged parts show 0.32V minimum voltage at 490kHz and up to 17X energy gain per operation. The memory terrestrial radiation Soft Error Rate was characterized with no multibit errors reported, enabling future medical appplications radiation reliability through bit-interleaving combined with error correcting code.

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“…This situation becomes a major challenge to reduce the leakage current as we have no option but to keep the circuit ON. To overcome the limitations mentioned above, the proposed SRAM cell has been equipped with a different read process which limits the time required to read the cell and helps in prohibiting the data corruption of cell by isolating it from the external read circuitry [6]. The cell has been designed to work with lower supply voltages, which helps in further reduction of the leakage power thus making the cell more efficient.…”

Section: Introductionmentioning

confidence: 99%

Design and analysis of different types SRAM cell topologies

Kiran¹,

Saxena²

2015

2015 2nd International Conference on Electronics and Communication Systems (ICECS)

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In this paper, we design different type of SRAM cells. This paper compares the performance of five SRAM cell topologies, which include the conventional 6T, 7T, 8T, 9T and the 10T SRAM cell implementations. In particular, the leakage currents, leakage power and read behaviour of each SRAM cells are examined. In 10T SRAM cell implementation results, reduced leakage power and leakage current by 36% and 64% respectively, the read stability is increased by 13% over conventional 6T, 7T, 8T and 9T SRAM cells. As a result, the 10T SRAM always consumes lowest leakage power and leakage current; improve read stability as compared to the 6T, 7T, 8T and 9T SRAM cells. The aim of this paper is to reduce the leakage power, leakage current and improve the read behaviour of the different SRAM cell structures using cadence tool at 45nm technology while keeping the read and write access time and the power as low as possible.

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A 1.85fW/bit ultra low leakage 10T SRAM with speed compensation scheme

Cited by 26 publications

References 9 publications

Low Power Design for Future Wearable and Implantable Devices

Low Power Design for Future Wearable and Implantable Devices

A 0.32V, 55fJ per bit access energy, CMOS 65nm bit-interleaved SRAM with radiation Soft Error tolerance

Design and analysis of different types SRAM cell topologies

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