A 0.03- to 3.6-GHz Frequency Synthesizer With Self-Biased VCO and Quadrature-Input Quadrature-Output Frequency Divider

Hu, Ang; Li, Dongsheng; Zhang, Kefeng

doi:10.1109/tcsii.2019.2899506

Cited by 12 publications

(5 citation statements)

References 9 publications

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“…The proposed self-biased circuit is shown in Figure 3. N[0], N [1], N [2], N [3], N [4], N [5], N [6], and N [7] are the corresponding bits of the 8-bit programmable frequency divider. The current I 1 is related to I 0 by…”

Section: The Self-biased Circuitmentioning

confidence: 99%

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A Novel Self-Biased Phase-Locked Loop Scheme for WLAN Applications

Tian

et al. 2021

Electronics

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This article presents a novel self-biased phase-locked loop (PLL) scheme for wireless local area network (WLAN) applications. A novel self-biased circuit that contains a current mirror circuit and a variable resistor circuit related to the frequency division ratio are proposed. The proposed self-biased PLL scheme achieves a fixed damping factor. Moreover, the self-biased technology allows the PLL loop bandwidth to track the input reference frequency and division ratio. The proposed start-up circuit speeds up the locking of the PLL. In addition, the proposed differential-to-single-ended (DTS) converter can guarantee a 50% duty cycle without operating the PLL at twice the chip operating frequency. The proposed self-biased PLL is implemented in a Semiconductor Manufacturing International Corporation (SMIC) 55 nm CMOS process. The measured root-mean-square jitter (RMS-jitter) integrated of PLL is 2.4 ps with a dissipation of 8.6 mW, and the resulting figure-of-merit is −223.05 dBc/Hz.

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Section: The Self-biased Circuitmentioning

confidence: 99%

“…PLL is a closed-loop feedback system [5][6][7]. The loop bandwidth and damping factor of the PLL will affect the PLL loop characteristics, such as the stability and locking time [8][9][10].…”

Section: Introductionmentioning

confidence: 99%

A Novel Self-Biased Phase-Locked Loop Scheme for WLAN Applications

Tian

et al. 2021

Electronics

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“…A typical PLL tends to lock on the target state at a roughly constant speed due to the fixed bandwidth. The self-biased PLLs, which find the optimal operating bias level and charge pump (CP) current in an adaptive fashion [1,2], feature high stability, low jitter, and large operation range, and have been widely used [3][4][5][6]. Further, the self-biased PLLs are in no need of resistors and are independent of operating process, voltage, temperature (PVT) and frequency.…”

Section: Introductionmentioning

confidence: 99%

A 1-to-3 GHz 5-to-512 Multiplier Adaptive Fast-Locking Self-Biased PLL in 28 nm CMOS

Wang

Yang

Jia³

2022

Electronics

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Based on a self-biased architecture, this paper presents a novel adaptive fast-locking, wide operating range and low-jitter phase-locked loop (PLL). A current injection and adaptive bandwidth technology with minimum area overhead is employed to speed up the loop equilibrium acquisition process, without any adverse impact on the steady-state loop dynamics and the jitter performance. The proposed start-up circuit resets the loop to an appropriate initial state in order to shorten the initial ramp-up interval of the voltage-controlled oscillator (VCO), also resulting in cutting down the pull-in time. In addition, a proportional factor is introduced to give some kind of flexibility in the circuit design optimization. The proposed adaptive fast-locking self-biased PLL (AFL-SPLL) is designed and realized in a prototype based on TSMC 28 nm CMOS process, having a supply voltage of 0.9 V and an area of 0.0281 mm2. This PLL demonstrates a tuning range of 1 to 3 GHz and power consumptions from 0.91 mW at 1 GHz to 4.6 mW at 3 GHz operating frequency. The experimental results show that the capture process has been accelerated by up to 84.7% over large division ratios, yet the capture performance did not deteriorate at all for small division ratios. Meanwhile, the circuit implementation gave almost no area increase and yet achieved a reduction in the lock-in time of about 6.5 times, namely from 23.5 μs (without the adaptive locking) to only 3.6 μs (with the adaptive locking) on the maximum operation frequency condition of 3 GHz.

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“…The self-biased proposed in [2][3] , which can choose the optimal operating bias level and charge pump current adaptively, can solve the problems mentioned above. The self-biased PLLs have advantages in stability, low jitter, process independence and large operation range, which are widely used even now, such as in [4][5][6].…”

Section: Introductionmentioning

confidence: 99%

A 3-6GHz 5-to-512 Multiplier Adaptive Fast-Locking Self-Biased PLL in 28nm CMOS

Wang

Yang

Jia

2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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This paper presents a design approach for fastlocking and low jitter self-biased phase-locked loop (PLL). The charge-pump current injection technology with minimum area overhead is adopted to accelerate the loop equilibrium capture process without sacrificing the jitter performance. A start-up circuit is proposed in order to shorten the initial ramping up interval of the voltage-controlled oscillator (VCO), which will also help in reducing the lock-in time. A proportional coefficient is introduced in designing self-biased PLLs, which provides more flexibility regarding practical circuits design. The proposed fastlocking self-biased PLL is designed in a TSMC 28nm CMOS process with a supply voltage of 0.9 V. The simulation results show that the locking time is reduced by up to 85% for large division ratios and should not deteriorate the capture performance in small division ratios. Meanwhile, the system almost has no increase in area and the locking time is reduced from 24us to about 3us when operating at 6GHz.

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A 0.03- to 3.6-GHz Frequency Synthesizer With Self-Biased VCO and Quadrature-Input Quadrature-Output Frequency Divider

Cited by 12 publications

References 9 publications

A Novel Self-Biased Phase-Locked Loop Scheme for WLAN Applications

A Novel Self-Biased Phase-Locked Loop Scheme for WLAN Applications

A 1-to-3 GHz 5-to-512 Multiplier Adaptive Fast-Locking Self-Biased PLL in 28 nm CMOS

A 3-6GHz 5-to-512 Multiplier Adaptive Fast-Locking Self-Biased PLL in 28nm CMOS

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