A 3-6GHz 5-to-512 Multiplier Adaptive Fast-Locking Self-Biased PLL in 28nm CMOS

Abstract

This paper presents a design approach for fastlocking and low jitter self-biased phase-locked loop (PLL). The charge-pump current injection technology with minimum area overhead is adopted to accelerate the loop equilibrium capture process without sacrificing the jitter performance. A start-up circuit is proposed in order to shorten the initial ramping up interval of the voltage-controlled oscillator (VCO), which will also help in reducing the lock-in time. A proportional coefficient is introduced in designing self-biased PLLs, which provides more flexibility regarding practical circuits design. The proposed fastlocking self-biased PLL is designed in a TSMC 28nm CMOS process with a supply voltage of 0.9 V. The simulation results show that the locking time is reduced by up to 85% for large division ratios and should not deteriorate the capture performance in small division ratios. Meanwhile, the system almost has no increase in area and the locking time is reduced from 24us to about 3us when operating at 6GHz.

A 0.9 V wideband SPLL with an adaptive fast‐locking circuit achieving 24.68 µs settling time reduction

“…Proposed AFLCC loop and CP circuit: In typical SPLLs, the pull-in process becomes slower as the N increases. To reduce the locking time for a large N, the AFLCC based on bandwidth tracking technique has been proposed in the previous paper [6,7], as shown in Figure 2, which generates and applies an adaptive current I LOCK in light of the phase error on the CP to widen the bandwidth. Under the framework of the AFLCC, this letter further proposes an improved self-biased CP, which is compatible with the AFLCC's operations and consequently reduces the CP switching noise.…”

Design and Analysis of the Self-Biased PLL with Adaptive Calibration for Minimum of the Charge Pump Current Mismatch

“…All the voltage biases of the PLL are generated by the additional internal and no bandgap reference voltage source. The charge pump current is set to multiplied x of buffer bias current, which is given by [11]:…”