A supply and temperature fluctuation compensation technique is proposed
to solve the gain fluctuation of the residual voltage dynamic amplifier
used in pipeline analog-to-digital converter (ADC). Combining slave
amplifier with the positive temperature coefficient (PTAT) voltage
generation circuit, the gain of the amplifier under different
temperature is calibrated adaptively without any complex hardware. At
the same time, PTAT can also compensate the fluctuation voltage of power
supply then the voltage gain of the amplifier is kept. The design is
simulated with 40nm process, the voltage gain variation is less than
1.9% in -40℃~80℃ and 1.4% at the supply voltage range
of 1.05V to 1.15V.
A digital adaptive mismatch calibration (DAMC) circuit is proposed to decrease the output jitter of phase-locked loop (PLL). After amplifying the phase error with a linear time amplifier (TA), the DAMC adopts a successive approximation pulse width calibration method to reduce the mismatch current of the charge pump. The PLL prototype is fabricated in a 40nm process, the static phase error of the proposed PLL can be reduced from 358 ps to 10 ps at a 50 MHz reference clock approximately, and the RMS jitter of the PLL output is reduced from 4.91 ps to 3.59 ps, and the extended DAMC area only occupies 1.3% of the whole PLL area.
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