A Novel Self-Biased Phase-Locked Loop Scheme for WLAN Applications

Abstract

This article presents a novel self-biased phase-locked loop (PLL) scheme for wireless local area network (WLAN) applications. A novel self-biased circuit that contains a current mirror circuit and a variable resistor circuit related to the frequency division ratio are proposed. The proposed self-biased PLL scheme achieves a fixed damping factor. Moreover, the self-biased technology allows the PLL loop bandwidth to track the input reference frequency and division ratio. The proposed start-up circuit speeds up the locking of the PLL. In addition, the proposed differential-to-single-ended (DTS) converter can guarantee a 50% duty cycle without operating the PLL at twice the chip operating frequency. The proposed self-biased PLL is implemented in a Semiconductor Manufacturing International Corporation (SMIC) 55 nm CMOS process. The measured root-mean-square jitter (RMS-jitter) integrated of PLL is 2.4 ps with a dissipation of 8.6 mW, and the resulting figure-of-merit is −223.05 dBc/Hz.

Design of a fully integrated VHF CP‐PLL frequency synthesizer with an all‐digital defect‐oriented built‐in self‐test

“…PLL since its inception has been integral, especially in communication technology. In recent times, its advancements in integrated circuit (IC) technology have made it an indispensable tool in areas such as wireless systems [20], micro-electromechanical systems (MEMS) [21], consumer electronics [22], motor control [23], and many more. PLL employs a negative feedback architecture that enables the economic multiplication of crystal frequencies by larger variable numbers.…”

A Wideband PLL with Adaptive Fast-Locking Current Circuit for Bandwidth Tracking and Settling Time Reduction

“…However, the lock time is not improved because its loop bandwidth cannot scale with the input frequency. Adaptive bandwidth control techniques are attractive for facilitating locking process and have been used in ring-oscillator based self-biased PLLs [2][3], but the locking latency caused by large division ratio effect still exists. Although, [4] provides an initialization circuit to speed up the VCO oscillation, reducing power-up latency is challenging, particularly when the target frequency is low.…”

“…During the settling process, this AFLCC injects an adaptive extra current (I lock ) into the CP to widen the bandwidth. BothI CP , I lock are adaptive and can be determined using Equation (3). By using this approach, the AFLCC can significantly reduce the settling time.…”

A 0.9 V Wideband SPLL With an Adaptive Fast-Locking Circuit Achieving 24.68 μs Settling Time Reduction

“…However, the lock time is not improved because its loop bandwidth cannot scale with the input frequency. Adaptive bandwidth control techniques are attractive for facilitating the locking process and have been used in ring-oscillator-based self-biased PLLs [2][3], but the locking latency caused by the large division ratio effect still exists. Although, [4] provides an initialization circuit to speed up the VCO oscillation, reducing power-up latency is challenging, particularly when the target frequency is low.…”

“…To reduce the locking time over large N, the AFLCC based on bandwidth tracking and adaptive current injection is proposed. During the settling process, this AFLCC injects an extra currentI LOCK into the CP to widen the bandwidth.I CP , I LOCK are adaptive and can be determined using Equation (3). For more flexibility in circuit optimization, the coefficient ( 1N ) is updated to (h/N ).…”