A 0.0021 mm<sup>2</sup>1.82 mW 2.2 GHz PLL Using Time-Based Integral Control in 65 nm CMOS

Zhu, Junheng; Nandwana, Romesh Kumar; Shu, Guanghua; Elkholy, Ahmed; Kim, Seong Joong; Hanumolu, Pavan Kumar

doi:10.1109/jssc.2016.2598768

Cited by 26 publications

(11 citation statements)

References 9 publications

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“…The results show that the circuit is capable of generating a 2GHz clock signal while dissipating only 412µW from a 1.8V supply. This translates to a FoM of 4.89GHz/mW, which compares favourably with other contemporary designs [5], [6]. Fig.…”

Section: Postlayout Simulation Resultssupporting

confidence: 58%

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Intermittent Excitation of High-Q Resonators for Low-Power High-Speed Clock Generation

Schormans

Valente

Demosthenous

2018

2018 IEEE International Symposium on Circuits and Systems (ISCAS)

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There is growing demand for circuits that can provide ever greater performance from a minimal power budget. Example applications include wireless sensor nodes, mobile devices, and biomedical implants. High speed clock circuits are an integral part of such systems, playing roles such as providing digital processor clocks, or generating wireless carrier signals; this clock generation can often take a large part of a system's power budget. Common techniques to reduce power consumption generally involve reducing the clock speed, and/or complex designs using a large circuit area. This paper proposes an alternative method of clock generation based on driving a high-Q resonator with a periodic chain of impulses. In this way, power consumption is reduced when compared to traditional resonator based designs; this power reduction comes at the cost of increased period jitter. A circuit was designed and laid out in 0.18µm CMOS, and was simulated in order to test the technique. Simulation results suggest that the circuit can achieve a FoM of 4.89GHz/mW, with a peak period jitter of 10.2ps at 2.015GHz, using a model resonator with a Q-factor of 126.

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Section: Postlayout Simulation Resultssupporting

confidence: 58%

“…For the case of a high speed clock, for example 2.4GHz for a WiFi carrier, DCOs require similar amounts of power as cross-coupled LC oscillators or PLLbased designs, which usually require several mW. Even in the case of an aggressively scaled low-power PLL circuit [6], the power consumption is still 1.82mW at 2.2GHz.…”

Section: Introductionmentioning

confidence: 99%

Intermittent Excitation of High-Q Resonators for Low-Power High-Speed Clock Generation

Schormans

Valente

Demosthenous

2018

2018 IEEE International Symposium on Circuits and Systems (ISCAS)

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“…The sensing circuitry is made of an XOR gate whose inputs are the SPADs' anodes. To have identical propagation delays for both inputs, we implemented a 16-transistor XOR gate by splitting each pull-up and pull-down path in two paths, where the transistors' positions are swapped, to guarantee that the output transition always involves the same number of transistors and sees the same internal node capacitances [29]. This solution effectively removes any deterministic skew between the two inputs.…”

Section: A Photodetectormentioning

confidence: 99%

Large-Area, Fast-Gated Digital SiPM With Integrated TDC for Portable and Wearable Time-Domain NIRS

Conca

Sesta

Buttafava

et al. 2020

IEEE J. Solid-State Circuits

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We present the design and characterization of a large-area, fast-gated, all-digital single-photon detector with programmable active area, internal gate generator, and time-todigital converter (TDC) with a built-in histogram builder circuit, suitable for performing high-sensitivity time-domain nearinfrared spectroscopy (TD-NIRS) measurements when coupled with pulsed laser sources. We used a novel low-power differential sensing technique that optimizes area occupation. The photodetector is a time-gated digital silicon photomultiplier (dSiPM) with an 8.6-mm 2 photosensitive area, 37% fill-factor, and ∼300 ps (20%-80%) gate rising edge, based on low-noise single-photon avalanche diodes (SPADs) and fabricated in 0.35-µm CMOS technology. The built-in TDC with a histogram builder has a least-significant-bit (LSB) of 78 ps and 128 time-bins, and the integrated circuit can be interfaced directly with a low-cost microcontroller with a serial interface for programming and readout. Experimental characterization demonstrated a temporal response as good as 300-ps full-width at half-maximum (FWHM) and a dynamic range >100 dB (thanks to the programmable active area size). This microelectronic detector paves the way for a miniaturized, stand-alone, multi-wavelength TD-NIRS system with an unprecedented level of integration and responsivity, suitable for portable and wearable systems. Index Terms-Digital silicon photomultiplier (dSiPM), fastgated single-photon avalanche diode (SPAD) array, photon counting, time-to-digital converter (TDC), time-domain near-infrared spectroscopy (TD-NIRS). I. INTRODUCTION T IME-DOMAIN near-infrared spectroscopy (TD-NIRS) is a powerful technique for obtaining non-invasive, in vivo measurements of tissue constituents and structure [1]. This can be exploited in many scientific fields, from a clinical Manuscript

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“…Hence, the Ring-VCO based PLL is preferable in applications due to its small area, wide range of tuning property, high insensitivity to magnetic coupling, and easy integration. The poor jitter performance of the Ring-VCO based PLL, however, brings difficulties in providing high quality clocks [6,7,8,9].…”

Section: Introductionmentioning

confidence: 99%

A wideband low-jitter PLL with an optimized Ring-VCO

Zou

Ren

Zou

2020

IEICE Electron. Express

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A wideband low-jitter phase-locked loop (PLL) is proposed to provide high performance clocks for the transceivers. The ring voltagecontrolled oscillator (Ring-VCO) is a key component of a PLL, which directly determine the out-band phase noise and output frequency range of the PLL. Therefore, a low phase noise two-stage Ring-VCO with a novel delay cell is proposed to help achieve a wideband low-jitter PLL. An accumulation-mode MOS (AMOS) varactor pair is adopted in the delay cell to improve the fine tuning linearity. Moreover, an additional AMOS varactor pair is employed to reduce the VCO gain variation in the coarse tuning process and enhance the tolerance in temperature and voltage variations. Implemented in a conventional TSMC 180 nm CMOS process, the proposed Ring-VCO can tune from 0.73 to 1.92 GHz and the worstcase phase noise at 1 MHz offset is −102 dBc/Hz. The output frequency range of the proposed PLL is 0.06-1.92 GHz and the RMS jitter is less than 3.8 ps over the whole working band.

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A 0.0021 mm²1.82 mW 2.2 GHz PLL Using Time-Based Integral Control in 65 nm CMOS

Cited by 26 publications

References 9 publications

Intermittent Excitation of High-Q Resonators for Low-Power High-Speed Clock Generation

Intermittent Excitation of High-Q Resonators for Low-Power High-Speed Clock Generation

Large-Area, Fast-Gated Digital SiPM With Integrated TDC for Portable and Wearable Time-Domain NIRS

A wideband low-jitter PLL with an optimized Ring-VCO

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A 0.0021 mm21.82 mW 2.2 GHz PLL Using Time-Based Integral Control in 65 nm CMOS

Cited by 26 publications

References 9 publications

Intermittent Excitation of High-Q Resonators for Low-Power High-Speed Clock Generation

Intermittent Excitation of High-Q Resonators for Low-Power High-Speed Clock Generation

Large-Area, Fast-Gated Digital SiPM With Integrated TDC for Portable and Wearable Time-Domain NIRS

A wideband low-jitter PLL with an optimized Ring-VCO

Contact Info

Product

Resources

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A 0.0021 mm²1.82 mW 2.2 GHz PLL Using Time-Based Integral Control in 65 nm CMOS