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Design of a processor optimized for syntax parsing in video decoders

“…The hardware implementation of an ASIP consists of a general processor with the addition of specific instructions within the ALU, or functional units within the core [4,5]. In short, the software implementation consists in updating the cross compilation tools, usually GCC/GDB.…”

“…Real-time video decoding is difficult to achieve on embedded processors because it requires an efficient implementation and a high-performance processor or DSP [5,8]. Usually, one or more coprocessors are implemented in addition with the processors to process algorithms that required high performance, like the Inverse Discrete Cosine Transform or the bitstream parsing (i.e.…”

“…To read an arbitrary number of bits from a bitstream, the usual methodology (which is described in the standard) consists of coding and using a ShowNbits function based on bit manipulation operations [5]. However, these operations are not well supported by common general-purpose processor architectures.…”

“…Researchers have presented methods to efficiently manage bit manipulation operations with results obtained on general purpose processor architectures [8], DSPs [1,5] or applications without real-time constraints [4]. This leads to a lack of exploration of real-time applications implemented on codesign architectures even though they are more and more used.…”

“…Part of the M-bits word is transfered from a global register into a showbits register. The transfer is done according to the location to keep only the required bits (others are consequently removed), 5. the required N bits are right shifted, 6.…”