A Heterogeneous Embedded MPSoC for Multimedia Applications

Yuan, Hong; Wang, Zhiying; Dai, Kui

doi:10.1007/11847366_61

Cited by 3 publications

(4 citation statements)

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“…A design can integrate multiple programmable cores, which (1) are individually optimized to a particular characteristic of different application fields in order to deliver high performance, and (2) complement each other with flexibility at reduced system cost. These designs are often referred to as heterogeneous MPSoCs [42,61,79,80,92].…”

Section: Multi-processor Socsmentioning

confidence: 99%

“…To further increase performance without substantially increasing power consumption parallel processing can be used at the instruction level (e.g., VLIW [27]) and at the data level (e.g., SIMD [65]). Furthermore, multi-processor SoCs (MPSoCs) start becoming popular [26,37,49,61,79,80,92]. As multi-processing is a very power-efficient way to increase processing capabilities [13], we expect there will be more and more processing units in the future.…”

Section: Multi-processor Socsmentioning

confidence: 99%

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Trend and Challenge on System-on-a-Chip Designs

Chen

Kung

2007

J Sign Process Syst Sign Image Video Technol

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The success of system-on-a-chip (SoC) hinges upon a well-concerted integrated approach from multiple disciplines, such as device, design, and application. From the device perspective, rapidly improving VLSI technology allows the integration of billions of transistors on a single chip, thus permitting a wide range of functions to be combined on one chip. From the application perspective, numerous killer applications have been identified, which can make full use of the aforementioned functionalities provided by a single chip. From the design perspective, however, with greater device integration, system designs become more complex and are increasingly challenging to design. Moving forward, novel approaches will be needed to meet these challenges. This paper explores several new design strategies, which represent the current design trends to deal with the emerging issues. For example, recognizing the stringent requirements on power consumption, memory bandwidth/ latency, and transistor variability, novel power/thermal management, multi-processor SoC, reconfigurable logic, and design for verification and testing have now been incorporated into modern system design. In addition, we look into some plausible solutions. For example, further innovations on scalable, reusable, and reliable system architectures, IP deployment and integration, on-chip interconnects, and memory hierarchies are all anticipated in the near future.

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Section: Multi-processor Socsmentioning

confidence: 99%

Section: Multi-processor Socsmentioning

confidence: 99%

Trend and Challenge on System-on-a-Chip Designs

Chen

Kung

2007

J Sign Process Syst Sign Image Video Technol

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“…[7,9]. In heterogeneous MPSoCs, the tiles are different, see examples in [11][12][13][14][15][16]. Particularly in multimedia applications, programmable general-purpose cores can be integrated with memories and with co-processors for computing intensive applications.…”

Section: Introductionmentioning

confidence: 99%

Design of a Wideband Antenna for Wireless Network-On-Chip in Multimedia Applications

Gutiérrez¹

2017

JLPEA

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Abstract:To allow fast communication-at several Gb/s-of multimedia content among processors and memories in a multi-processor system-on-chip, a new approach is emerging in literature: Wireless Network-on-Chip (WiNoC). With reference to this scenario, this paper presents the design of the key element of the WiNoC: the antenna. Specifically, a bow-tie antenna is proposed, which operates at mm-waves and can be implemented on-chip using the top metal layer of a conventional silicon CMOS (Complementary Metal Oxide Semiconductor) technology. The antenna performance is discussed in the paper and is compared to the state-of-the-art, including the zig-zag antenna topology that is typically used in literature as a reference for WiNoC. The proposed bow-tie antenna design for WiNoC stands out for its good trade-off among bandwidth, gain, size and beamwidth vs. the state-of-the-art.

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“…Processors embedded on the single chip do not need to be the same type. An efficient way is to arrange specific processors perform some sophisticated and frequently-occurring functions [39,40,41,42].…”

Section: Future System-on-a-chip Design Trendsmentioning

confidence: 99%

System-on-a-Chip (SoC) based Hardware Acceleration in Register Transfer Level (RTL) Design

Niu¹

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Today, modern System-on-a-Chip (SoC) systems have grown rapidly due to the increased processing power, while maintaining the size of the hardware circuit. The number of transistors on a chip continues to increase, but current SoC designs may not be able to exploit the potential performance, especially with energy consumption and chip area becoming two major concerns. Traditional SoC designs usually separate software and hardware. Thus, the process of improving the system performance is a complicated task for both software and hardware designers. The aim of this research is to develop hardware acceleration workflow for software applications. Thus, system performance can be improved with constraints of energy consumption and on-chip resource costs. The characteristics of software applications can be identified by using profiling tools.Hardware acceleration can have significant performance improvement for highly mathematical calculations or repeated functions. The performance of SoC systems can then be improved, if the hardware acceleration method is used to accelerate the element that incurs performance overheads. The concepts mentioned in this study can be easily applied to a variety of sophisticated software applications. viiThe contributions of SoC-based hardware acceleration in the hardware-software co-design platform include the following: (1) Software profiling methods are applied to H.264 Coder-Decoder (CODEC) core. The hotspot function of aimed application is identified by using critical attributes such as cycles per loop, loop rounds, etc. (2) Hardware acceleration method based on Field-Programmable Gate Array (FPGA) is used to resolve system bottlenecks and improve system performance. The identified hotspot function is then converted to a hardware accelerator and mapped onto the hardware platform. Two types of hardware acceleration methods -central bus design and coprocessor design, are implemented for comparison in the proposed architecture. (3) System specifications, such as performance, energy consumption, and resource costs, are measured and analyzed. The trade-off of these three factors is compared and balanced.Different hardware accelerators are implemented and evaluated based on system requirements. 4) The system verification platform is designed based on Integrated Circuit (IC) workflow. Hardware optimization techniques are used for higher performance and less resource costs.Experimental results show that the proposed hardware acceleration workflow for software applications is an efficient technique. The system can reach 2.8X performance improvements and save 31.84% energy consumption by applying the Bus-IP design. The Co-processor design can have 7.9X performance and save 75.85% energy consumption. viii MotivationSince the invention of modern computers from the middle of the twentieth century, semiconductor manufacturers have focused mainly on processing as much information as possible while maintaining or minimizing the execution time. In addition, as technology evolves, the size of the tran...

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A Heterogeneous Embedded MPSoC for Multimedia Applications

Cited by 3 publications

References 4 publications

Trend and Challenge on System-on-a-Chip Designs

Trend and Challenge on System-on-a-Chip Designs

Design of a Wideband Antenna for Wireless Network-On-Chip in Multimedia Applications

System-on-a-Chip (SoC) based Hardware Acceleration in Register Transfer Level (RTL) Design

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