9.8 A 25mm<sup>2</sup> SoC for IoT Devices with 18ms Noise-Robust Speech-to-Text Latency via Bayesian Speech Denoising and Attention-Based Sequence-to-Sequence DNN Speech Recognition in 16nm FinFET

Tambe, Thierry; Yang, En-Yu; Ko, Glenn G.; Chai, Yuji; Hooper, Coleman; Donato, Marco; Whatmough, Paul N.; Rushton, Gérard; Brooks, David; Wei, Gu-Yeon

doi:10.1109/isscc42613.2021.9366062

Cited by 25 publications

(9 citation statements)

References 4 publications

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“…Some simulation statistics are not reported by the designers (N/A). keypair [58], gsm [59], HLSCNN [60], FlexNLP [61], Dataflow [62], and Opticalflow [63] do not feature any subaccelerators with a batch size greater than one. One OOB bug was found in gsm and one initialization bug was found in keypair.…”

Section: Appendix D Results (Extended)mentioning

confidence: 99%

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Scaling Up Hardware Accelerator Verification using A-QED with Functional Decomposition

Chattopadhyay,

Lonsing,

Piccolboni

et al. 2021

Preprint

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Hardware accelerators (HAs) are essential building blocks for fast and energy-efficient computing systems. Accelerator Quick Error Detection (A-QED) is a recent formal technique which uses Bounded Model Checking for pre-silicon verification of HAs. A-QED checks an HA for self-consistency, i.e., whether identical inputs within a sequence of operations always produce the same output. Under modest assumptions, A-QED is both sound and complete. However, as is well-known, large design sizes significantly limit the scalability of formal verification, including A-QED. We overcome this scalability challenge through a new decomposition technique for A-QED, called A-QED with Decomposition (A-QED 2 ). A-QED 2 systematically decomposes an HA into smaller, functional sub-modules, called sub-accelerators, which are then verified independently using A-QED. We prove completeness of A-QED 2 ; in particular, if the full HA under verification contains a bug, then A-QED 2 ensures detection of that bug during A-QED verification of the corresponding subaccelerators. Results on over 100 (buggy) versions of a wide variety of HAs with millions of logic gates demonstrate the effectiveness and practicality of A-QED 2 . This article will appear in the proceedings of Formal Methods in Computer-Aided Design (FMCAD 2021).

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Section: Appendix D Results (Extended)mentioning

confidence: 99%

“…Average runtimes result from dividing the time to detect all bugs by the number of bugs. † keypair[58], gsm[59], HLSCNN[60], FlexNLP[61], Dataflow[62], and Opticalflow[63] all time out for A-QED FC and do not contain any sub-accelerators with batch size greater than one. One OOB bug was detected in gsm and one initialization bug in keypair.…”

mentioning

confidence: 99%

Scaling Up Hardware Accelerator Verification using A-QED with Functional Decomposition

Chattopadhyay,

Lonsing,

Piccolboni

et al. 2021

Preprint

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“…The current existing deep learning accelerators [3]- [7], [21] are usually designed to meet high-performance needs with large number of processing elements and different data flows. However, these state-of-the-art hardware accelerators have low hardware utilization while executing the time-domain separation model including the four main key operations of the 1-D convolution, the 1-D depthwise dilated convolution, 1-D 1×1 convolution and 1-D transposed convolution.…”

Section: Deep Learning Acceleratorsmentioning

confidence: 99%

A 1.6-mW Sparse Deep Learning Accelerator for Speech Separation

Yang

Chang

2023

IEEE Trans. VLSI Syst.

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Low power deep learning accelerators on the speech processing enable real-time applications on edge devices. However, most of the existing accelerators suffer from high power consumption and focus on image applications only. This paper presents a low power accelerator for speech separation through algorithm and hardware optimizations. At the algorithm level, the model is compressed with structured sensitivity as well as unstructured pruning, and further quantized to the shifted 8-bit floating-point format instead of the 32-bit floating-point format. The computations with the zero kernel and zero activation values are skipped by decomposition of the dilated and transposed convolutions. At the hardware level, the compressed model is then supported by an architecture with eight independent multipliers and accumulators (MACs) with a simple zero-skipping hardware to take advantage of the activation sparsity and low power processing. The proposed approach reduces the model size by 95.44% and computation complexity by 93.88%. The final implementation with the TSMC 40 nm process can achieve real-time speech separation and consumes 1.6 mW power when operated at 150 MHz. The normalized energy efficiency and area efficiency are 2.344 TOPS/W and 14.42 GOPS/mm 2 , respectively.

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“…To achieve high robustness KWS, one method is to include all the possible SNR levels and noise types in the AI model training, which causes the increasing of model size and is challenging for ultra-low-power applications. To overcome the noise problem in KWS, Wang [2] employed a simpler voice extracting method called divisive energy normalization (DN), and developed a normalized acoustic feature extractor chip (NAFE) for analog signal processing. The frontend of NAFE is composed by a low-noise amplifier (LNA), a bandpass filter (BFP), a half-wave rectifier (HWR) and an integrate-and-fire (IAF) encoder, and extract the pre-normalized features (preNF).…”

Section: Ai Chips For Voice Applicationsmentioning

confidence: 99%

Trending IC design directions in 2022

Chan¹,

Cheng²,

Deng³

et al. 2022

J. Semicond.

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For the non-stop demands for a better and smarter society, the number of electronic devices keeps increasing exponentially; and the computation power, communication data rate, smart sensing capability and intelligence are always not enough. Hardware supports software, while the integrated circuit (IC) is the core of hardware. In this long review paper, we summarize and discuss recent trending IC design directions and challenges, and try to give the readers big/cool pictures on each selected small/hot topics. We divide the trends into the following six categories, namely, 1) machine learning and artificial intelligence (AI) chips, 2) communication ICs, 3) data converters, 4) power converters, 5) imagers and range sensors, 6) emerging directions. Hope you find this paper useful for your future research and works.

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9.8 A 25mm² SoC for IoT Devices with 18ms Noise-Robust Speech-to-Text Latency via Bayesian Speech Denoising and Attention-Based Sequence-to-Sequence DNN Speech Recognition in 16nm FinFET

Cited by 25 publications

References 4 publications

Scaling Up Hardware Accelerator Verification using A-QED with Functional Decomposition

Scaling Up Hardware Accelerator Verification using A-QED with Functional Decomposition

A 1.6-mW Sparse Deep Learning Accelerator for Speech Separation

Trending IC design directions in 2022

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9.8 A 25mm2 SoC for IoT Devices with 18ms Noise-Robust Speech-to-Text Latency via Bayesian Speech Denoising and Attention-Based Sequence-to-Sequence DNN Speech Recognition in 16nm FinFET

Cited by 25 publications

References 4 publications

Scaling Up Hardware Accelerator Verification using A-QED with Functional Decomposition

Scaling Up Hardware Accelerator Verification using A-QED with Functional Decomposition

A 1.6-mW Sparse Deep Learning Accelerator for Speech Separation

Trending IC design directions in 2022

Contact Info

Product

Resources

About

9.8 A 25mm² SoC for IoT Devices with 18ms Noise-Robust Speech-to-Text Latency via Bayesian Speech Denoising and Attention-Based Sequence-to-Sequence DNN Speech Recognition in 16nm FinFET