760 MHz G6 S/390 microprocessor exploiting multiple Vt and copper interconnects

McPherson, T.; Averill, R.M.; Balazich, D.; Barkley, K.; Carey, Seán; Chan, Yiu-Hing; Crea, R.; Dansky, A.H.; Dwyer, Robert S.; Haen, A.-M.; Hoffman, D.; Jatkowski, Adam; Mayo, M.; Merrill, D.; McNamara, T.; Northrop, G. A.; Rawlins, John Clayton; Sigal, L.; Slegel, T. J.; Webber, Daniel; Williams, Paul; Yee, Fanchieh

doi:10.1109/isscc.2000.839707

Cited by 14 publications

(7 citation statements)

References 2 publications

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“…In subthreshold region the performance of the adders is degraded making it unsuitable for signal/data processing. In order to improve the performance in subthreshold region, forward body bias (FBB) [9]- [12] and multi threshold transistor (MVT) techniques [3]- [4] are used. This research conducts a quantitative power-performance analysis of the Kogge-Stone adder using 45nm bulk CMOS technology in typical-typical (TT), slow-slow (SS) and fast-fast (FF) corners at various operating temperatures.…”

Section: Introductionmentioning

confidence: 99%

An Ultra-Low Power Robust Koggestone Adder at Sub-Threshold Voltages for Implantable Bio-Medical Devices

Nanduru¹,

Koppa²,

John³

2017

VLSICS

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Section: Introductionmentioning

confidence: 99%

An Ultra-Low Power Robust Koggestone Adder at Sub-Threshold Voltages for Implantable Bio-Medical Devices

Nanduru¹,

Koppa²,

John³

2017

VLSICS

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“…This is chosen because of the commercial work-loads that the z990 processor targets. This FXU design is the first superscalar processor for the CMOS z-series servers [2] [and has many other enhanced features over preceding designs [3][4][5]. These features include operand forwarding, condition code forwarding, muti-port instruction dispatch, enhanced decimal performance and a binary multiplier.…”

Section: Introductionmentioning

confidence: 99%

The design of the fixed point unit for the z990 microprocessor

Busaba

Slegel

Carlough

et al. 2004

Proceedings of the 14th ACM Great Lakes Symposium on VLSI

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The paper presents the design of the Fixed Point Unit (FXU) for the IBM eServer z990 microprocessor (announced in 2Q '03) that runs at 1.2 GHz [2]. The FXU is capable of executing two Register-Memory instructions including arithmetic instructions and a branch instruction in a single cycle. The FXU executes a total of 369 instructions that operate on variable size operands (1 to 256 bytes). The instruction set include decimal arithmetic with multiplies and divides, binary arithmetic, shifts and rotates, loads/stores, branches, long moves, logical operations, convert instructions, and other special instructions. The FXU consists of 64-bit dataflow stack that is custom designed and a control stack that is synthesized. The current FXU is the first superscalar design for the CMOS z-series machines, has a new improved decimal unit, and has for the first time a 16x64 bit binary multiplier.

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“…Techniques that trade increased circuit delay for reduced leakage current include: conventional transistor sizing, lower Vdd [32,30], stacked gates [25,35,9], longer channels [23], higher threshold voltages [19,34,21,13,1], and thicker T ox ; we collectively refer to these as statically-selected slow transistors (SSSTs). Techniques for dynamic run-time deactivation of fast transistors include body biasing [24,17,18,20,15], sleep transistors [24,29,13,11,16], and sleep vectors [35,9]; we collectively refer to these as dynamically-deactivated fast transistors (DDFTs).…”

Section: Introductionmentioning

confidence: 99%