Digest. International Electron Devices Meeting,
DOI: 10.1109/iedm.2002.1175851
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75 nm damascene metal gate and high-k integration for advanced CMOS devices

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Cited by 43 publications
(17 citation statements)
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“…Measurements of hysteresis and PBTI have been performed on Nmos of two stacks families: the first one [3] uses ALCVD-HfO 2 with two different thicknesses (3 and 4.5 nm) deposited on a 0.7 nm native oxide and annealed (PDA) under nitrogen ambient at 600°C or 800°C. Final eot (equivalent oxide thickness) is in the range 1.5-2.5 nm..…”
Section: Devices and Hysteresis Experimentsmentioning
confidence: 99%
See 1 more Smart Citation
“…Measurements of hysteresis and PBTI have been performed on Nmos of two stacks families: the first one [3] uses ALCVD-HfO 2 with two different thicknesses (3 and 4.5 nm) deposited on a 0.7 nm native oxide and annealed (PDA) under nitrogen ambient at 600°C or 800°C. Final eot (equivalent oxide thickness) is in the range 1.5-2.5 nm..…”
Section: Devices and Hysteresis Experimentsmentioning
confidence: 99%
“…Hafnium-based dielectrics are the best candidates today for gate insulators of future CMOS technologies [1][2][3]. However, some limitations remain to be minimized: mobility degradation, apparent metal gate potential instability during processing, threshold voltage instabilities [4][5][6] at t 0 called hysteresis [7], threshold voltage instabilities during the life of the device (reliability).…”
Section: Introductionmentioning
confidence: 99%
“…Как показано в экспериментальных работах [22][23][24], поверхностная подвижность носителей в МОП-структурах с подзатворным диэлектриком, в состав которого входит HfO 2 , значительно меньше, чем в МОП-структурах с подзатворным диэлектриком SiO 2 . На рис.1 приведено сравнение эффективной подвижности в МОП-структурах с диэлек-триками HfO 2 и SiO 2 .…”
Section: таблица 1 набор физических моделей для описания High-k мопт-unclassified
“…Various fabrication techniques of grooved gate/RC MOSFETs [7,18,19] and multilayered gate dielectric architecture [20,21] have been reported in the literature. Further, several integration schemes for workfunction engineered gate electrodes have already been suggested in past such as tilt angle evaporation metal gate deposition [14], metal interdiffusion process [22,23], fully silicided metal gate [24], chemical mechanical polishing [25] and II method poly-Si gate doping control [26]. With the CMOS processing technology already into the 85 nm regime [27], fabricating a 50-nm gate length MLGEWE-RC MOSFET should not encumber the possibility of realizing the substantial performance gains that the MLGEWE-RC MOSFET assures.…”
Section: Introductionmentioning
confidence: 99%