7.4 Gb/s 6.8 mW Source Synchronous Receiver in 65 nm CMOS

Hossain, Masum; Carusone, Anthony Chan

doi:10.1109/jssc.2011.2131730

Cited by 30 publications

(14 citation statements)

References 12 publications

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“…However, the JTB of an ILO depends strongly on clock deskew, making it difficult to achieve both the optimal JTB and optimal deskew simultaneously [6]. To solve this problem, multiplying ILO (MILO)-local ILO (LILO) [8] and ILO with a JTB interpolator [9] are presented.…”

Section: Architecture Reviewmentioning

confidence: 99%

A 9.6-Gb/s 1.22-mW/Gb/s Data-Jitter Mixing Forwarded-Clock Receiver in 65-nm CMOS

Chung

Kim

2015

IEEE Trans. VLSI Syst.

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In this paper, a data-jitter mixing (DJM) forwardedclock receiver is proposed that achieves high jitter correlation between data and a clock for high speed and small power consumption. The first-stage injection-locked oscillator (ILO) filters out high-frequency clock jitter that loses the correlation due to a latency mismatch between data and the clock. Then, a data-jitter mixer in the second stage of the proposed receiver further increases the jitter correlation reduced by nonoptimal jitter filtering in ILO. Moreover, the DJM reduces power supply noise induced jitter from a clock distribution network, while the conventional jitter filter cannot track the high-frequency jitter because of filtering it out. A prototype receiver implemented in 1-V 65-nm CMOS process achieves 9.6 Gb/s with 1.22-mW/Gb/s in spite of a 1.92-ns latency mismatch between data and a clock.Index Terms-Data-jitter mixer (DJM), double-balanced mixer, injection-locked oscillator (ILO), jitter tracking bandwidth, receiver, source synchronous parallel link.

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Section: Architecture Reviewmentioning

confidence: 99%

A 9.6-Gb/s 1.22-mW/Gb/s Data-Jitter Mixing Forwarded-Clock Receiver in 65-nm CMOS

Chung

Kim

2015

IEEE Trans. VLSI Syst.

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“…One of the main advantages of forwarded clock architectures is that the clock and data channels are clocked by the same transmit oscillator, and therefore, some of the jitter is correlated and tracks each other. However, on one hand, due to the delay mismatch between the clock and data channels, high frequency jitter will become harmful, because clock and data will be eventually out-of-phase [6], [19], which means ILO bandwidth should be low enough so as not to track high frequency jitter. On the other hand, since ILO is like a first-order PLL, it will low-pass filter the noise from the injection clock, and high-pass filter the noise from itself [5].…”

Section: B Trade-offs In Forwarded-clock Architecture Using Ilomentioning

confidence: 99%

“…Therefore, ILO bandwidth should also be high enough to suppress the phase noise from itself. In practical designs, this direct trade-off leads to ILO bandwidth in the range of several ten to several hundred MHz [5], [6], depending on different environment or applications.…”

Section: B Trade-offs In Forwarded-clock Architecture Using Ilomentioning

confidence: 99%

“…In these designs, sample clock phase deskew is achieved using phase interpolators with delay-locked loops (DLLs) [2] or phase-rotating phase-locked loops (PLLs) [3]. Relative to conventional phase interpolators, injection-locked oscillators (ILOs) [4]- [6] have been introduced as an energy-efficient technique for deskewing the phase positions of sampling clocks.…”

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confidence: 99%

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0.16-0.25 pJ/bit, 8 Gb/s Near-Threshold Serial Link Receiver With Super-Harmonic Injection-Locking

Bai

Jiang

et al. 2012

IEEE J. Solid-State Circuits

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Abstract-A near-threshold forwarded-clock I/O receiver architecture is presented. In the proposed receiver, the majority of the circuitry is designed to operate in the near-threshold region at 0.6 V supply to save power, with the exception of only the global clock buffer, test buffers and synthesized digital circuits at the nominal 1 V supply. To ensure the quantizers are working properly with this low supply, a 1:10 direct demultiplexing rate is chosen as a demonstration of achieving low supply operation by high-parallelism. A novel low-power super-harmonic injection-locked ring oscillator is proposed to generate deskewable symmetric multi-phase local clock phases. The relative performance impact of including a perdata lane sample-and-hold (S/H) to improve quantizer aperture time at low voltage is demonstrated with two receiver prototypes fabricated in a 65 nm CMOS technology. Including the amortized power of global clock distribution, the receiver without S/H consumes 1.3 mW and the one with S/H consumes 2 mW at an 8 Gb/s input data rate, which converts to 0.163 pJ/bit and 0.25 pJ/bit, respectively. Measurement results show both receivers get BER 10 across a 20-cm FR4 PCB channel.

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“…The MIPI-DigRF M-PHY should be operated in 3 symbol interval (SI) training time which is very short compared with other interfaces such as display port [4][5][6][7]. The length of the SYNC pattern is 3 SI (= 30 UI (unit intervals)), which is 0.01 μs in HS-G2B mode.…”

Section: Introductionmentioning

confidence: 99%

A 1.248 Gb/s - 2.918 Gb/s Low-Power Receiver for MIPI-DigRF M-PHY with a Fast Settling Fully Digital Frequency Detection Loop in 0.11 ㎛ CMOS

Kim¹,

Lee²,

Park³

et al. 2015

JSTS:Journal of Semiconductor Technology and Science

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7.4 Gb/s 6.8 mW Source Synchronous Receiver in 65 nm CMOS

Cited by 30 publications

References 12 publications

A 9.6-Gb/s 1.22-mW/Gb/s Data-Jitter Mixing Forwarded-Clock Receiver in 65-nm CMOS

A 9.6-Gb/s 1.22-mW/Gb/s Data-Jitter Mixing Forwarded-Clock Receiver in 65-nm CMOS

0.16-0.25 pJ/bit, 8 Gb/s Near-Threshold Serial Link Receiver With Super-Harmonic Injection-Locking

A 1.248 Gb/s - 2.918 Gb/s Low-Power Receiver for MIPI-DigRF M-PHY with a Fast Settling Fully Digital Frequency Detection Loop in 0.11 ㎛ CMOS

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