0.16-0.25 pJ/bit, 8 Gb/s Near-Threshold Serial Link Receiver With Super-Harmonic Injection-Locking

Abstract

Abstract-A near-threshold forwarded-clock I/O receiver architecture is presented. In the proposed receiver, the majority of the circuitry is designed to operate in the near-threshold region at 0.6 V supply to save power, with the exception of only the global clock buffer, test buffers and synthesized digital circuits at the nominal 1 V supply. To ensure the quantizers are working properly with this low supply, a 1:10 direct demultiplexing rate is chosen as a demonstration of achieving low supply operation by high-parallelism. A novel low-power super-harmonic injection-locked ring oscillator is proposed to generate deskewable symmetric multi-phase local clock phases. The relative performance impact of including a perdata lane sample-and-hold (S/H) to improve quantizer aperture time at low voltage is demonstrated with two receiver prototypes fabricated in a 65 nm CMOS technology. Including the amortized power of global clock distribution, the receiver without S/H consumes 1.3 mW and the one with S/H consumes 2 mW at an 8 Gb/s input data rate, which converts to 0.163 pJ/bit and 0.25 pJ/bit, respectively. Measurement results show both receivers get BER 10 across a 20-cm FR4 PCB channel.

A 0.8V, 560fJ/bit, 14Gb/s injection-locked receiver with input duty-cycle distortion tolerable edge-rotating 5/4X sub-rate CDR in 65nm CMOS

“…Furthermore, operating the high-speed transceiver at a lower supply voltage can dramatically improve the energy efficiently due to the quadratic dependency on V DD , at the cost of degraded transistor speed and increased timing uncertainty. While speed limitations can be overcome with increased receiver input de-multiplexing ratios [1], timing uncertainties caused by low-V DD operation (static phase mismatches and temperature/low-frequency power-supply induced jitter) remain significant challenges to the widespread adoption of low-V DD serial links. This work presents a low-voltage quarter-rate forwarded-clock receiver that utilizes a low overhead edge-rotating 5/4X sub-rate CDR that improves jitter tolerance and enables automatic independent phase rotator control to optimize timing margin of each input quantizer in the presence of receive-side clock static phase errors and transmitter duty-cycle distortion (DCD).…”