6.4 A 180mW 56Gb/s DSP-Based Transceiver for High Density IOs in Data Center Switches in 7nm FinFET Technology

Today’s computing challenges: opportunities for computer hardware design

“…However, the interconnect partially takes advantage of the technology scaling, because faster transistors enable a better circuit to overcome the increased channel loss. Figure 11A shows a survey from the state-of-the-art published works ( Tamura et al, 2001 ; Haycock & Mooney, 2001 ; Tanaka et al, 2002 ; Lee et al, 2003 , 2004 ; Krishna et al, 2005 ; Landman et al, 2005 ; Casper et al, 2006 ; Palermo, Emami-Neyestanak & Horowitz, 2008 ; Kim et al, 2008 ; Lee, Chen & Wang, 2008 ; Amamiya et al, 2009 ; Chen et al, 2011 ; Takemoto et al, 2012 ; Raghavan et al, 2013 ; Navid et al, 2014 ; Zhang et al, 2015 ; Upadhyaya et al, 2015 ; Norimatsu et al, 2016 ; Gopalakrishnan et al, 2016 ; Shibasaki et al, 2016 ; Peng et al, 2017 ; Han et al, 2017 ; Upadhyaya et al, 2018 ; Wang et al, 2018 ; Depaoli et al, 2018 ; Tang et al, 2018 ; LaCroix et al, 2019 ; Pisati et al, 2019 ; Ali et al, 2019 , 2020 ; Im et al, 2020 ; Yoo et al, 2020 ), where we can confirm the correlation between the technology node and the data rate. On the other hand, however, overcoming the increased channel loss has become more and more expensive as the loss is going worse as the bandwidth increases; the equalization circuits consume too much power to compensate the loss, which makes people hesitant to increase the bandwidth.…”

“…Recently, a dramatic change has been made to break the ice. An amplitude modulation technique, which is called 4-level pulse-amplitude modulation (PAM-4), has been adopted in the industry ( Upadhyaya et al, 2018 ; Wang et al, 2018 ; Depaoli et al, 2018 ; Tang et al, 2018 ; LaCroix et al, 2019 ; Pisati et al, 2019 ; Ali et al, 2019 , 2020 ; Im et al, 2020 ; Yoo et al, 2020 ). With PAM-4, the interconnect can transmit two bits in one-bit period, which doubles the effective bandwidth over NRZ.…”

“…On the other hand, we can also make a bigger change on the architecture. In an analog-to-digital converter (ADC)-based interconnect or digital signal processing (DSP)-based interconnect ( LaCroix et al, 2019 ; Pisati et al, 2019 ; Ali et al, 2019 ; 2020 ; Im et al, 2020 ; Yoo et al, 2020 ; Harwood et al, 2007 ; Chen & Yang, 2010 ; Wang et al, 2018 ; Palermo et al, 2018 ), the analog front-end circuits of the receiver are replaced by a high-speed ADC, and a large fraction of the equalization and CDR stuffs are done in the digital domain. With that, an extensive equalization with dense digital logic is enabled.…”

Design Space Exploration of Single-Lane OFDM-Based Serial Links for High-Speed Wireline Communications

“…While the dominating modulation scheme for serial links with data rate up to 56 Gb/s has been non-return-to-zero (NRZ) [9]- [12], 4-level pulse-amplitude modulation (PAM-4) started to be dominating from per-lane data rate of 56 Gb/s to reduce the maximum channel loss that the signal experiences at Nyquist [13]- [17]. Despite the increased circuit complexity and latency coming from the additionally required forward error correction (FEC), recently demonstrated 112 Gb/s TRXs [6]- [8] employ PAM-4 due to its 2× better bandwidth efficiency as compared to that of NRZ, with an analog-to-digital converter (ADC)-based RX front-end with heavy equalization on the digital signal processor (DSP).…”

A 25Gb/s 185mW PAM-4 Receiver with 4-Tap Adaptive DFE and Sampling Clock Optimization in 55nm CMOS

“…As the demand of bandwidth increases, multi-PAM signaling such as PAM-4 has emerged as a solution for the next generation of high-speed wireline transceivers owing to the lower Nyquist frequency and higher power efficiency [1][2][3][4]. Nevertheless, the sampling phase is more critical for PAM-4 signaling as the eye width and eye height is much smaller compared to NRZ due to the fourlevel modulation [2]. The inter-symbol-interference (ISI) due to the multi-level transitions results in less eye width.…”