5T SRAM With Asymmetric Sizing for Improved Read Stability

Nalam, Satyanand; Calhoun, Benton H.

doi:10.1109/jssc.2011.2160812

Cited by 37 publications

(23 citation statements)

References 35 publications

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“…Thus by doing this the read stability problem in conventional 6T SRAM cell is avoided and better read stability is retained in conventional 8T SRAM cell. The read stack and the use of short local bit lines, the 8T can provide high performance [4].…”

Section: Conventional 8t Sram Cellmentioning

confidence: 99%

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Power and Area Efficient 10t Sram With Improved Read Stability

Geethumol¹,

S²,

Dhanusha³

2017

IJME

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In this paper, a 10T Static Random Access Memory bit cell is proposed to meet design specification for performance, stability, area and power consumption. In every state of SRAM cell designs low power and increased noise margin plays an important role. The conventional 6T SRAM cell is very much prone to noise during read operation. In order to overcome the Read SNM problem in the 6T SRAM cell designers have implemented many other SRAM configurations such as 8T, 9T, 10T. These SRAM cell configurations improve the read stability but increase the power consumption. We proposed a 10T SRAM cell which can solve all these problems by introducing the transmission gate and using stacking effect in the configuration. In this paper different SRAM cells analyzed on the basis of power and read stability and we proposed a 1-bit SRAM memory array using the proposed 10T SRAM bit cell that achieves cell stability, lower power consumption and lesser area. The proposed circuit was implemented in Mentor Graphics Design Architect, simulated using Mentor Graphics ELDO at supply voltage of 1.8V with the help of TSMC 180nm technology. Micro wind is used to draw layout of SRAM cells and peripherals.

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Section: Conventional 8t Sram Cellmentioning

confidence: 99%

“…Shirked transistor sizes and reduced power supply voltages lead to lower noise margin. Due to these problems, devices more sensitive to noise sources [4]. This prevents the scaling of the conventional 6T SRAM bit-cell to lower supply voltages and to newer technology.…”

Section: Introductionmentioning

confidence: 99%

Power and Area Efficient 10t Sram With Improved Read Stability

Geethumol¹,

S²,

Dhanusha³

2017

IJME

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“…1 have been removed to provide a five-transistor configuration. The removal of such access transistor allows for an area savings up to 20-30% compared to the standard 6T SRAM cell, while its power consumption is substantially reduced by one half [9]. Although the traditional 5T SRAM cells offer such significant reductions in power consumption, a serious drawback is presented in that it is difficult to write '1' to the cells.…”

Section: Existing 6t and 5t Sram Cell Topologiesmentioning

confidence: 99%

“…Some of these techniques rely on boosted word line voltage [10]- [12], reducing the supply voltage VDD [8]- [9], [13]- [14], sizing cell transistors [15]- [17], reduced bit line voltage [18]- [19], and raising the source voltage V SS [20]- [22]. However, each of these techniques may cause a reduction in the drive current of the transistors and in the operating speed of the cell, or has increased memory cell area and a degradation in the manufacturing accuracy, or requires generation of a voltage above the operating voltage, or requires a more complicated circuit design and more complicated device process.…”

Section: Existing 6t and 5t Sram Cell Topologiesmentioning

confidence: 99%

Single-Port 5T SRAM Cell with Improved Write-Ability and Reduced Standby Leakage Current

Yu¹,

Shiau²

2017

IJIEE

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Abstract-In this paper, a novel single-port five-transistor (5T) Static Random Access Memory (SRAM) cell and associated read/write assist is proposed. Amongst them, a voltage level conversion circuit is to provide a voltage of the respective connected word line to be lower than or equal to the power supply voltage VDD, as such the read/write-ability of the cell can be improved. Furthermore, a voltage control circuit is coupled to the sources corresponding to the driver transistors of each row memory cells. This configuration is aimed to control the source voltages of driver transistors under different operating modes. In addition, a pre-charging circuit is design to pull up the bit line BL of a selected column to the voltage VDD before the read or write operation. Finally, with the standby start-up circuit design, the memory cell can rapidly switch to the standby mode, and thereby reduce leakage current in standby. In particular, the paper introduce a two-phase reading mechanism to improve the reading speed, and thus to avoid unnecessary power consumption. Furthermore, by using the voltage level conversion circuit to pull the voltage of the signal WLC in a selected row cells lower than the power supply voltage VDD by a threshold voltage during a read operation, thereby to reduce the half-selected cells disturbance.Index Terms-Read/write assist circuitry, standby start-up circuit, static random access memory, voltage level conversion circuit, voltage control circuit.

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“…Larger cell topologies, such as 8T register file cells [14], and 10T cells with column interleaving support [15], provide improved cell stability at the expense of area and power by decoupling read and write operations. Literature also includes more exotic examples of asymmetrical cells, such as 5T [16], and 7T [17], cells. Another significant design centric solution involved the change from a ''tall'' to a ''wide'' cell design [18].…”

Section: Low Power Memory Design Trendsmentioning

confidence: 99%

A survey of cross-layer power-reliability tradeoffs in multi and many core systems-on-chip

Eltawil

Engel

Geuskens

et al. 2013

Microprocessors and Microsystems

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a b s t r a c tAs systems-on-chip increase in complexity, the underlying technology presents us with significant challenges due to increased power consumption as well as decreased reliability. Today, designers must consider building systems that achieve the requisite functionality and performance using components that may be unreliable. In order to do so, it is crucial to understand the close interplay between the different layers of a system: technology, platform, and application. This will enable the most general tradeoff exploration, reaping the most benefits in power, performance and reliability. This paper surveys various cross layer techniques and approaches for power, performance, and reliability tradeoffs are technology, circuit, architecture and application layers.

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5T SRAM With Asymmetric Sizing for Improved Read Stability

Cited by 37 publications

References 35 publications

Power and Area Efficient 10t Sram With Improved Read Stability

Power and Area Efficient 10t Sram With Improved Read Stability

Single-Port 5T SRAM Cell with Improved Write-Ability and Reduced Standby Leakage Current

A survey of cross-layer power-reliability tradeoffs in multi and many core systems-on-chip

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