5nm FinFET Standard Cell Library Optimization and Circuit Synthesis in Near-and Super-Threshold Voltage Regimes

Abstract

FinFET device has been proposed as a promising substitute for the traditional bulk CMOS-based device at the nanoscale, due to its extraordinary properties such as improved channel controllability, high ON/OFF current ratio, reduced short-channel effects, and relative immunity to gate line-edge roughness. In addition, the near-ideal subthreshold behavior indicates the potential application of FinFET circuits in the nearthreshold supply voltage regime, which consumes an order of magnitude less energy than the regular strong-inversion circuits operating in the super-threshold supply voltage regime. This paper presents a design flow of creating standard cells by using the FinFET 5nm technology node, including both near-threshold and super-threshold operations, and building a Liberty-format standard cell library. The circuit synthesis results of various combinational and sequential circuits based on the 5nm FinFET standard cell library show up to 40X circuit speed improvement and three orders of magnitude energy reduction compared to those of 45nm bulk CMOS technology.

Multi-Functional Resource-Constrained Elliptic Curve Cryptographic Processor

“…The ScalingFactor for 90-nm, 65-nm, and 45-nm CMOS technology are 6.6, 12, and 19, respectively. The authors in [51] The area is nearly the same as ours, but it could perform only NIST P-163, while our design could perform up to NIST P-521. We also compare the ADP of our design and other proposals to evaluate the effectiveness of our processor.…”

“…The design is placed and routed with ROHM 180nm CMOS technology. In order to perform a fair comparison, the area and maximum working frequency are converted to the corresponding value with ROHM 180-nm technology depending on the report [51], [52]. Depending on [51], the area scale is calculated by the formula 1.…”

“…In order to perform a fair comparison, the area and maximum working frequency are converted to the corresponding value with ROHM 180-nm technology depending on the report [51], [52]. Depending on [51], the area scale is calculated by the formula 1. Where the Area 180nm is the corresponding area of the design when using 180nm CMOS technology, Area target is the area of the design when using other CMOS technology, and the ScalingFactor is defined by [51].…”

“…Depending on [51], the area scale is calculated by the formula 1. Where the Area 180nm is the corresponding area of the design when using 180nm CMOS technology, Area target is the area of the design when using other CMOS technology, and the ScalingFactor is defined by [51]. The ScalingFactor for 90-nm, 65-nm, and 45-nm CMOS technology are 6.6, 12, and 19, respectively.…”