5GHz 32b integer-execution core in 130nm dual-V/sub T/ CMOS

Vangal, Sriram; Borkar, Nitin; Seligman, Erik; Govindarajulu, V.; Erraguntla, Vasantha; Wilson, H.; Pangal, A.; Veeramachaneni, V.; Anders, M.; Tschanz, J.; Ye, Y.; Somasekhar, D.; Bloechel, B.; Dermer, G.; Krishnamurthy, R.; Narendra, S.; Stan, M.; Thompson, S.; De, Vivek; Borkar, S.

doi:10.1109/isscc.2002.992282

Cited by 5 publications

(4 citation statements)

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“…As a result, the overall power savings achievable by clock gating alone is diminishing. Using dynamic powergating and body bias techniques, used in conjunction with clock gating can help to control the active leakage power of an ALU in a 32-bit integer execution core [Vangal et al 2002]. Performance impacts, area overheads, active leakage and total power reductions achievable by these techniques are measured on the prototype chip (Figure 34) implemented in a 130 nm dual-V t CMOS technology.…”

Section: Power Gatingmentioning

confidence: 99%

Challenges and design choices in nanoscale CMOS

Narendra

2005

J. Emerg. Technol. Comput. Syst.

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The driving force for the semiconductor industry growth has been the elegant scaling nature of CMOS technology. In this article, we will first review the history of technology scaling that follows Moore's law from the prespective of microprocessor designs. Challenges to continue the historical scaling trends will be highlighted and design choices to address two specific challenges, process variation and leakage power, will be discussed. In nanoscale CMOS technology generations, supply and threshold voltages will have to continually scale to sustain performance increase, limit energy consumption, control power dissipation, and maintain reliability. These continual scaling requirements on supply and threshold voltages pose several technology and circuit design challenges. One such challenge is the expected increase in process variation and the resulting increase in design margins. Concept of adaptive circuit schemes to deal with increasing design margins will be explained. Next, with threshold voltage scaling, subthreshold leakage power has become a significant portion of total power in nanoscale CMOS systems. Therefore, it has become imperative to accurately predict and minimize leakage power of such systems, especially with increasing within-die threshold voltage variation. A model that predicts system leakage based on first principles will be presented and circuit techniques to reduce system leakage will be discussed. It is essential to point out that this article does not cover all challenges that nanoscale CMOS systems face. Challenges that are not detailed in the main sections of the article and speculation on what future nanoscale silicon based CMOS systems might resemble are summarized.

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Section: Power Gatingmentioning

confidence: 99%

Challenges and design choices in nanoscale CMOS

Narendra

2005

J. Emerg. Technol. Comput. Syst.

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“…Register files (RF) are performance critical building blocks of highend microprocessors requiring single cycle read/write latency [12,13,21]. In this paper, we design low power word-line (WL) drivers using the above mentioned leakage control techniques for a 256entry 64-bit high-performance RF.…”

Section: Figure 1: I On /I Off and V Th Scaling For Sub-130nm Generatmentioning

confidence: 99%

Effectiveness and scaling trends of leakage control techniques for sub-130nm CMOS technologies

Chatterjee

Sachdev

Hsu

et al. 2003

Proceedings of the 2003 International Symposium on Low Power Electronics and Design - ISLPED '03

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This paper compares the effectiveness of different leakage control techniques in deep submicron (DSM) bulk CMOS technologies. Simulations show that the 3-5x increase in I OFF /µm per generation is offsetting the savings in switching energy obtained from technology scaling. We compare both the transistor I OFF reduction and I ON degradation due to each technique for the 130nm-70nm technologies. Our results indicate that the effectiveness of leakage control techniques and the associated energy vs. delay tradeoffs depend on the ratio of switching to leakage energies for a given technology. We use our findings to design a 70nm low power word line driver scheme for a 256 entry, 64-bit register file (RF). As a result, the leakage (total) energy of the word line drivers is reduced by 3x(2.5x) and for the RF by up to 35%(25%) respectively.

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“…Forward substrate bias is used during active operation in order to lower V TH for high-speed operation, and zero substrate bias during standby mode in order to raise V TH for low leakage. The substrate biasing technique has begun to be applied to high-end products such as microprocessors and communications chips for low-power, high-speed operation [8][9].…”

Section: Variable V Dd and V Thmentioning

confidence: 99%

Optimization and control of V_DD and V_TH for low-power, high-speed CMOS design

Kuroda

2002

Proceedings of the 2002 IEEE/ACM International Conference on Computer-Aided Design - ICCAD '02

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It is essential to control V DD and V TH for low-power, high-speed CMOS design. In this paper, it is shown that these two parameters can be controlled by designers as objectives of design optimization to find better trade-offs between power and speed. Quantitative analysis of trade-offs between power and speed is presented. Some of the popular circuit techniques and design examples to control V DD and V TH are introduced. A simple theory to compute optimum multiple V DD 's and V TH 's is described. Scaling scenarios of variable and/or multiple V DD 's and V TH 's is discussed to show future technology directions.

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5GHz 32b integer-execution core in 130nm dual-V/sub T/ CMOS

Cited by 5 publications

References 0 publications

Challenges and design choices in nanoscale CMOS

Challenges and design choices in nanoscale CMOS

Effectiveness and scaling trends of leakage control techniques for sub-130nm CMOS technologies

Optimization and control of V_DD and V_TH for low-power, high-speed CMOS design

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5GHz 32b integer-execution core in 130nm dual-V/sub T/ CMOS

Cited by 5 publications

References 0 publications

Challenges and design choices in nanoscale CMOS

Challenges and design choices in nanoscale CMOS

Effectiveness and scaling trends of leakage control techniques for sub-130nm CMOS technologies

Optimization and control of VDD and VTH for low-power, high-speed CMOS design

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Optimization and control of V_DD and V_TH for low-power, high-speed CMOS design