55 nm capacitor-less 1T DRAM cell transistor with non-overlap structure

Song, Ki–Whan; Jeong, Hoon; Lee, Jae‐Wook; Hong, Seong Wook; Tak, Nam-Kyun; Kim, Young-Tae; Choi, Yong Lack; Joo, Han Sung; Kim, Sung Hwan; Song, Hyo‐Jong; Oh, Youngtek; Kim, Woo-Seop; Lee, Yeong-Taek; Oh, Kyungseok; Kim, Changhyun

doi:10.1109/iedm.2008.4796818

Cited by 45 publications

(9 citation statements)

References 1 publication

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“…Extensionless devices reduce gate induced drain leakage and, therefore, improve the retention time as already reported [30,31]. Besides, from our study, the retention is due to hole generation mainly in the junctions space charge region and the electric field at the junction enhances this generation by including generation via trap assisted tunneling.…”

Section: Resultssupporting

confidence: 52%

Understanding and optimizing the floating body retention in FDSOI UTBOX

Aoulaiche¹,

Simoen

Caillat³

et al. 2016

Solid-State Electronics

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Section: Resultssupporting

confidence: 52%

Understanding and optimizing the floating body retention in FDSOI UTBOX

Aoulaiche¹,

Simoen

Caillat³

et al. 2016

Solid-State Electronics

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“…Conventional one-transistor one-capacitor dynamic random-access memory (1T-1C DRAM) has reached its scaling limit due to the difficulty of miniaturizing capacitors. Therefore, capacitor-less one-transistor dynamic random-access memory (1T-DRAM), which does not need complicated capacitor fabrication, has been studied as a possible replacement for 1T-1C DRAM [1][2][3][4][5][6][7][8][9][10][11][12][13][14]. 1T-DRAM can be densely integrated because it has a small 4F 2 cell size with a silicon-on-insulator (SOI) transistor as its basic structure.…”

Section: Introductionmentioning

confidence: 99%

Analysis of the Sensing Margin of Silicon and Poly-Si 1T-DRAM

et al. 2020

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Recently, one-transistor dynamic random-access memory (1T-DRAM) cells having a polysilicon body (poly-Si 1T-DRAM) have attracted attention as candidates to replace conventional one-transistor one-capacitor dynamic random-access memory (1T-1C DRAM). Poly-Si 1T-DRAM enables the cost-effective implementation of a silicon-on-insulator (SOI) structure and a three-dimensional (3D) stacked architecture for increasing integration density. However, studies on the transient characteristics of poly-Si 1T-DRAM are still lacking. In this paper, with TCAD simulation, we examine the differences between the memory mechanisms in poly-Si and silicon body 1T-DRAM. A silicon 1T-DRAM cell’s data state is determined by the number of holes stored in a floating body (FB), while a poly-Si 1T-DRAM cell’s state depends on the number of electrons trapped in its grain boundary (GB). This means that a poly-Si 1T-DRAM can perform memory operations by using GB as a storage region in thin body devices with a small FB area.

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“…Conventional one-transistor one-capacitor dynamic random-access memory (1T-1C DRAM) cells are severely limited in integration density because it is difficult to miniaturize their capacitors, so capacitorless 1T-DRAM has attracted attention as a promising alternative [1][2][3][4][5][6][7][8][9][10][11][12][13][14]. 1T-DRAM devices composed of one silicon-on-insulator (SOI) transistor have different operating mechanisms depending on their body material [15].…”

Section: Introductionmentioning

confidence: 99%

Analysis of a Lateral Grain Boundary for Reducing Performance Variations in Poly-Si 1T-DRAM

2020

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A capacitorless one-transistor dynamic random-access memory device that uses a poly-silicon body (poly-Si 1T-DRAM) has been suggested to overcome the scaling limit of conventional one-transistor one-capacitor dynamic random-access memory (1T-1C DRAM). A poly-Si 1T-DRAM cell operates as a memory by utilizing the charge trapped at the grain boundaries (GBs) of its poly-Si body; vertical GBs are formed randomly during fabrication. This paper describes technology computer aided design (TCAD) device simulations performed to investigate the sensing margin and retention time of poly-Si 1T-DRAM as a function of its lateral GB location. The results show that the memory’s operating mechanism changes with the GB’s lateral location because of a corresponding change in the number of trapped electrons or holes. We determined the optimum lateral GB location for the best memory performance by considering both the sensing margin and retention time. We also performed simulations to analyze the effect of a lateral GB on the operation of a poly-Si 1T-DRAM that has a vertical GB. The memory performance of devices without a lateral GB significantly deteriorates when a vertical GB is located near the source or drain junction, while devices with a lateral GB have little change in memory characteristics with different vertical GB locations. This means that poly-Si 1T-DRAM devices with a lateral GB can operate reliably without any memory performance degradation from randomly determined vertical GB locations.

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55 nm capacitor-less 1T DRAM cell transistor with non-overlap structure

Cited by 45 publications

References 1 publication

Understanding and optimizing the floating body retention in FDSOI UTBOX

Understanding and optimizing the floating body retention in FDSOI UTBOX

Analysis of the Sensing Margin of Silicon and Poly-Si 1T-DRAM

Analysis of a Lateral Grain Boundary for Reducing Performance Variations in Poly-Si 1T-DRAM

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