50% active-power saving without speed degradation using standby power reduction (SPR) circuit

Seta, K.; Hara, Hiroyuki; Kuroda, Tadahiro; Kakumu, M.; Sakurai, Takayasu

doi:10.1109/isscc.1995.535572

Cited by 52 publications

(20 citation statements)

References 2 publications

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“…There are various methods to reduce leakage using these bodybiasing techniques. RBB can be applied in sleep mode to reduce subthreshold leakage [Seta et al 1995]; a circuit can be designed with V t higher than its initial target value, and then FBB is applied in active mode to compensate for the large initial delay, while zero body bias is applied in sleep mode ] to reduce the leakage; or a circuit can be designed with V dd lower than its initial target value, and then FBB is used in active mode to compensate, which reduces sleep power consumption because of the lower V dd . RBB becomes less effective with technology scaling due to a steepening increase in junction leakage [Keshavarzi et al 1999] with the extent of the biasing.…”

Section: Low-leakage Circuitsmentioning

confidence: 99%

Power gating

Shin

Seomun

Choi

et al. 2010

ACM Trans. Des. Autom. Electron. Syst.

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Power gating has become one of the most widely used circuit design techniques for reducing leakage current. Its concept is very simple, but its application to standard-cell VLSI designs involves many careful considerations. The great complexity of designing a power-gated circuit originates from the side effects of inserting current switches, which have to be resolved by a combination of extra circuitry and customized tools and methodologies. In this tutorial we survey these design considerations and look at the best practice within industry and academia. Topics include output isolation and data retention, current switch design and sizing, and physical design issues such as power networks, increases in area and wirelength, and power grid analysis. Designers can benefit from this tutorial by obtaining a better understanding of implications of power gating during an early stage of VLSI designs. We also review the ways in which power gating has been improved. These include reducing the sizes of switches, cutting transition delays, applying power gating to smaller blocks of circuitry, and reducing the energy dissipated in mode transitions. Power gating has also been combined with other circuit techniques, and these hybrids are also reviewed. Important open problems are identified as a stimulus to research.

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Section: Low-leakage Circuitsmentioning

confidence: 99%

Power gating

Shin

Seomun

Choi

et al. 2010

ACM Trans. Des. Autom. Electron. Syst.

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“…Because of the large capacitance and distributed resistance of the wells, charging or discharging the well has a relatively high time constant and dissipates considerable energy. To allow the latency and energy costs of transitioning into the low leakage state to be amortized, these schemes are used when the processor enters a sleep state where it will be idle for at least 0.1-100 µs [28,17,30].…”

Section: Dynamically-deactivated Fast Transistorsmentioning

confidence: 99%

Dynamic fine-grain leakage reduction using leakage-biased bitlines

Heo¹,

Barr²,

Hampton³

et al. 2002

SIGARCH Comput. Archit. News

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“…The transfer function of this flow is given by Y=X+(EI+Eq)/( 1 -z-'Hf)=X+( 1 -z-')(Eq+EI). (2) This equation shows that the latch-error noise (El) is shaped by the quantizing noise and the new signal flow achieves the S/N performance without latch-error noise. Therefore, it is possible to achieve a high S/N ratio even (1) though the data latch timing of the DAC is set before the maximum comparison time, and this setting makes the feedback loop stable.…”

Section: Introductionmentioning

confidence: 99%

“…Lowering the supply voltage is the most effective way to achieve lowpower performance because power consumption decreases approximately in proportion to the square of the supply voltage. Some digital circuit techniques that lower the supply voltage to that provided by a one cell battery (1.2 V) have been reported [1] [2]. Similarly, highaccuracy A/D and D/A converters operating at a 1.2-V supply are required for analog interfaces due to enable the use of a single power supply line.…”

Section: Introductionmentioning

confidence: 99%