5.5GHz system z microprocessor and multi-chip module

Warnock, J.; Chan, Yuen; Harrer, H.; Rude, D.; Puri, Ruchir; Carey, Seán; Salem, G.; Mayer, G.; Chan, Yiu-Hing; Mayo, M.; Jatkowski, Adam; Strevig, Gerald; Sigal, L.; Datta, Ayan; Gattiker, A.; Bansal, Aditya; Malone, D.; Strach, Thomas; Wen, Huajun; Mak, P.; Shum, C.-L. K.; Plass, D.; Webb, Charles F.

doi:10.1109/isscc.2013.6487630

Cited by 11 publications

(8 citation statements)

References 2 publications

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“…This design achieves a hydraulic diameter as large a 200µm. Warnock et al [88] describes a technique called the 5.5GHz System z Microprocessor and multi-chip module. This chip features a high-frequency processor core for running at 5.5GHz in a 32nm high-k CMOS technology using 15 levels of metal.…”

Section: Energy Saving Chipsmentioning

confidence: 99%

A Survey of Emerging Architectural Techniques for Improving Cache Energy Consumption

Bhebhe

Agyeman

2016

CAE

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Abstract-The search goes on for another ground breaking phenomenon to reduce the ever-increasing disparity between the CPU performance and storage. There are encouraging breakthroughs in enhancing CPU performance through fabrication technologies and changes in chip designs but not as much luck has been struck with regards to the computer storage resulting in material negative system performance. A lot of research effort has been put on finding techniques that can improve the energy efficiency of cache architectures. This work is a survey of energy saving techniques which are grouped on whether they save the dynamic energy, leakage energy or both. Needless to mention, the aim of this work is to compile a quick reference guide of energy saving techniques from 2013 to 2016 for engineers, researchers and students.

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Section: Energy Saving Chipsmentioning

confidence: 99%

A Survey of Emerging Architectural Techniques for Improving Cache Energy Consumption

Bhebhe

Agyeman

2016

CAE

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“…Each drawer consists of two tightly coupled processing nodes, up to 2.5 terabytes (TB) of physical memory, up to 4 legacy Galaxy (GX) I/O adapters, and 10 integrated PCIe** x16 Generation-3 I/O hubs [2], along with an enhanced four-level cache design. Combined, these features provide up to 50% more system capacity throughput than the IBM zEnterprise* EC12 (zEC12) [3,4]. In addition, these features enable the system to better support the traditional LSPR (Large Systems Performance Reference) workload set [5], to better leverage and expand on the hardware/ software synergy that emerged on the zEC12 system, and to provide a highly competitive system for new and emerging workloads, while continuing the trend for increased system capacity within a constant energy footprint from one generation of mainframe to the next [6].…”

Section: Introductionmentioning

confidence: 99%

The IBM z13 processor cache subsystem

et al. 2015

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“…The previous generation design, the IBM zEnterprise* EC12 (zEC12) [1][2][3] also relied on two chips, a processor chip and an L4 (Level 4) cache chip, both in 32-nm technology, with 2.7 and 3.3 billion transistors, respectively. The z13 design makes use of the improved density of the 22-nm technology and larger chip areas to greatly increase the overall device count and chip functionality, with about 4 and 7.1 billion transistors on the CP (Central Processor) and SC (System Controller) chips, respectively.…”

Section: Introductionmentioning

confidence: 99%