4H-SiC Planar MESFETs on High-Purity Semi-Insulating Substrates

Abstract

Planar MESFETs were fabricated on high-purity semi-insulating (HPSI) 4H-SiC substrates. The saturation drain current of the fabricated MESFETs with a gate length of 0.5 μm and a gate width of 100 μm was 430 mA/mm, and the transconductance was 25 mS/mm. The maximum oscillation frequency and cut-off frequency were 26.4 GHz and 7.2 GHz, respectively. The power gain was 8.4 dB and the maximum output power density was 2.8 W/mm for operation of class A at CW 2 GHz. MESFETs on HPSI substrates showed no current instability and much higher output power density in comparison to MESFETs on vanadium-doped SI substrates.

High Purity Semi-Insulating 4H-SiC Epitaxial Layers by Defect-Competition Epitaxy: Controlling Si Vacancies

“…2), close to the FWHM 6-8 arcsec of perfect SiC crystals 10 . This compares very favorably with recent results 11 showing FWHM of 18 arcsec for HPSI and 24 arcsec for V-doped SI.…”

“…A typical epilayer X-ray rocking curve full-width half maximum (FWHM) is $8 arcsec, 8) close to 6-8 arcsec for perfect SiC. 10) This compares very favorably with results 11) showing FWHM's of 18 arcsec for HPSI and 24 arcsec for V-doped SiC.…”

“…Although this is the originally conceived method of producing commercial SI substrates, reports 1) indicate that vanadium degrades the crystal quality. 11) The alternative is to pin the Fermi level deep in the bandgap by compensating shallow donors/acceptors from residual impurities with intrinsic deep defects. The development of such high-purity semi-insulating (HPSI) SiC was reported, 2) but determination of the exact nature of the defects and compensation mechanism are still in progress.…”

Fabrication and Testing of 4H-SiC MESFETs for Analog Functions Circuits

“…The best devices achieved a drain current density of roughly 50 mA/mm at V DS =20V and a transconductance of 3.55 mS (4.44 mS/mm) at V GS = -4 V in the saturation region. Lateral MESFET with shorter channel can achieve higher transconductance [4]. The benefits of the buried gate have been investigated with respect to changes in transconductance and in negative gate bias.…”

Parameter extraction procedure for high power SiC JFET

“…Generally, SiC device electrical models use an empirical expression for carrier mobility such as (1) [1,2], despite the fact that it is well known that this parameter may vary over quite a wide range, depending on processing parameters such as temperature, annealing conditions, defect density, stoichiometry, and so on [3,4]. …”