2010
DOI: 10.4028/www.scientific.net/msf.645-648.1159
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Fabrication and Testing of 4H-SiC MESFETs for Analog Functions Circuits

Abstract: Lateral normally-on dual gates MESFETs withstanding a drain/source voltage in excess of 200V have been fabricated on semi-insulating 4H-SiC substrate. This paper reports on the fabrication, DC characterization and in-circuit behavior of the MESFETs. Temperature dependent DC characterization has been carried out up to 473K. The performances of basic analog circuits such as an amplifier and a clock, using these MESFETs, are detailed and analyzed.

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Cited by 8 publications
(10 citation statements)
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“…The fabrication of 4H-SiC MESFET transistor using mesa isolation was already reported in [2] as having a proper behavior up to an ambient of 200ºC. In our previous work [3 were reported results up to 300ºC.…”
Section: Mesa Isolationmentioning
confidence: 96%
“…The fabrication of 4H-SiC MESFET transistor using mesa isolation was already reported in [2] as having a proper behavior up to an ambient of 200ºC. In our previous work [3 were reported results up to 300ºC.…”
Section: Mesa Isolationmentioning
confidence: 96%
“…With the mesa isolation technique, the 4H-SiC MESFETs have shown a proper behavior up to 300ºC [2]. This method has proved to assure a good isolation between devices and it is widely used for individual device definition due to its simplicity [3].…”
Section: The 4h-sic Device Librarymentioning
confidence: 98%
“…Therefore, some important and novel design and fabrication features have been considered in the development of the new structure: a) the P + -implanted walls isolation technique which, to our knowledge, has been utilized in SiC for the first time; b) the transistor layout approach (finger-gate), which is typically used in the Si-CMOS ICs; and c) the process flow is fully compatible with CMOS processes. The groundwork of the new planar-MESFET mainly relies on the electrical and geometrical analysis of the already fabricated mesa-MESFET [2].…”
Section: The 4h-sic Normally-on Planar-mesfetmentioning
confidence: 99%
“…Figure 2 shows the singular planar-MESFET layout (m=1), where the P + -implanted isolation (the red ring) can be observed. The gate electrode ratio W G /L G for the novel device is 48μm/8μm, being roughly 1/10 of the mesa-MESFETs [4]. However, the embraced geometry presents a built-in drain-to-source residual current at the ends of the metal finger-gate.…”
Section: B Transistor Layout Design and Device Scalabilitymentioning
confidence: 99%
“…The method used so far for SiC JFET and MESFET isolation is the mesa-etching technique [1,4], thanks to its well-known simplicity [5]. However, using this technique it becomes difficult to ensure reliable interconnections between devices, due to the non-planarity caused by the mesa-etch process.…”
Section: A P + -Implanted Walls Isolation Techniquementioning
confidence: 99%