Parameter extraction procedure for high power SiC JFET

Греков, A.; Chen, Ziyang; Santi, Enrico; Hudgins, J.L.; Mantooth, Alan; Sheridan, David C.; Casady, Jeff B.

doi:10.1109/ecce.2009.5316253

Cited by 12 publications

(4 citation statements)

References 8 publications

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“…The above relations for 𝑉𝑉 𝑡𝑡ℎ and 𝑅𝑅 𝑜𝑜𝑜𝑜 have been traditionally used e.g. [7], [8]. This demonstrates the compatibility of the new theoretical approach with established literature.…”

Section: Model Descriptionsupporting

confidence: 53%

Compact Modeling of SiC and GaN Junction FETs at High Temperature

Makris¹,

Zekentes

Bucher

2019

MSF

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High temperatures and other harsh environments are domains of predilection for Junction FETs, particularly when wide band-gap semiconductors such as SiC or GaN are used. The present work describes the new compact model of double gate (DG) JFETs which is compared to TCAD simulations of SiC and GaN JFETs over a wide temperature range up to 500oC. The compact model is shown to be predictive of device behavior, for static (current-voltage) as well as dynamic (capacitance-voltage) behavior of long-channel DG JFETs.

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Section: Model Descriptionsupporting

confidence: 53%

Compact Modeling of SiC and GaN Junction FETs at High Temperature

Makris¹,

Zekentes

Bucher

2019

MSF

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“…where ND is doping density, T is temperature of the channel. The decrease in the mobility due to the high thermal stress on the SiC JFET will result in an increase in RCH, as shown in (12) [40].…”

Section: A Reasons For Changes In Static Characteristicsmentioning

confidence: 99%

Investigation on the Degradation Mechanism of Si/SiC Cascode Device Under Repetitive Short-Circuit Tests

Zhang,

Liu,

Zhou

2024

IEEE Open J. Power Electron.

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The Si/SiC Cascode device has been widely accepted in various applications, however, its reliability issue still remains a major concern and needs to be extensively investigated. In this paper, the degradation of a 750 V Si/SiC Cascode device under repetitive short-circuit (SC) tests is investigated at 400 V DC-link voltage. Static and dynamic characteristics are measured before and after the repetitive SC cycles. As the SC cycle increases, the degradation of the device becomes gradually significant. By linking changes in electrical properties to metallization degradation, the physical mechanism of device degradation has been uncovered in depth. Experimental results show that the continuous stress under repetitive SC cycle leads to an increase in the on-state resistance of Si/SiC Cascode device. Finite-element-model (FEM) simulations show that due to the pad current crowding in the source region, the source Al metallization temperature of the SiC JFET rapidly increases to the melting point and undergoes reconstruction, resulting in a significant increase in the source Al metallization resistance. In addition, it is found by scanning electron microscopy (SEM) that the gate metal aluminum of SiC JFET chip also undergoes reconstruction, which is the reason for the degradation of the dynamic characteristics. The research in this paper will provide useful evidences for device manufactures to design Si/SiC Cascode device with high reliability.

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“…The original Shichman-Hodges model assumes [12] that the gate-source and the gate-drain junctions appearing in the transistor structure are identical in terms of physical properties and electrical parameters. Therefore, the model parameters such as M, PB and FC are used to describe properties of the junctions in common (see Equations (4)- (7)). This means that an attempt to determine the values of these parameters in order to achieve a good agreement between simulation and measurement results of the gate-drain junction automatically changes the shape of calculated gate-source junction characteristics.…”

Section: Modifications Of the Shichman-hodges Modelmentioning

confidence: 99%

“…A new generation of junction field-effect transistors made of silicon carbide (SiC-JFETs) has appeared on the market as a result of technological progress in the construction of semiconductor devices [1,3,5]. SiC-JFETs are characterized by better static properties, i.e., higher values of absolute maximum ratings of operating currents, terminal voltages and dissipated power as well as dynamic properties related to short switching times [5][6][7].…”

Section: Introductionmentioning

confidence: 99%

Modelling of Dynamic Properties of Silicon Carbide Junction Field-Effect Transistors (JFETs)

2020

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The paper deals with the problem of modelling and analyzing the dynamic properties of a Junction Field Effect Transistor (JFET) made of silicon carbide. An examination of the usefulness of the built-in JFET Simulation Program with Integrated Circuit Emphasis (SPICE) model was performed. A modified model of silicon carbide JFET was proposed to increase modelling accuracy. An evaluation of the accuracy of the modified model was performed by comparison of the measured and calculated capacitance–voltage characteristics as well as the switching characteristics of JFETs.

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Parameter extraction procedure for high power SiC JFET

Cited by 12 publications

References 8 publications

Compact Modeling of SiC and GaN Junction FETs at High Temperature

Compact Modeling of SiC and GaN Junction FETs at High Temperature

Investigation on the Degradation Mechanism of Si/SiC Cascode Device Under Repetitive Short-Circuit Tests

Modelling of Dynamic Properties of Silicon Carbide Junction Field-Effect Transistors (JFETs)

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