4H-SiC Full Wafer Mapping Image of CMP-Finished Sub-Surface Damage by Laser Light Scattering

Dojima, Daichi; Dansako, Daichi; Maki, Mizuho; Toda, Kohei; Kaneko, Tadaaki

doi:10.4028/p-1i3w12

Cited by 3 publications

(1 citation statement)

References 10 publications

(12 reference statements)

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“…[8][9][10] Therefore, development of wafer inspection technologies has been explored to screen through poor quality wafers. 7,[10][11][12][13][14][15][16][17][18] Over the past two decades, basal plane dislocations (BPDs) in 4H-SiC substrates have emerged as crucial defects in SiC wafers. Bipolar degradation in 4H-SiC PN diodes has emerged as a significant concern affecting their operational longevity.…”

Section: Introductionmentioning

confidence: 99%

Effects of proton implantation for expansion of basal plane dislocations in SiC toward suppression of bipolar degradation: review and perspective

Kato,

Harada,

Sakane

2024

Jpn. J. Appl. Phys.

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Silicon carbide (SiC) is widely used in power semiconductor devices; however, basal plane dislocations (BPDs) degrade device performance, through a mechanism called bipolar degradation. Recently, we proposed that proton implantation could suppress BPD expansion by reducing BPD mobility. We considered three potential mechanisms: the hydrogen presence around BPDs, point defects induced by implantation, and carrier lifetime reduction. In this study, we discuss the mechanisms of proton implantation and its applicability to SiC power device production.

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Section: Introductionmentioning

confidence: 99%

Effects of proton implantation for expansion of basal plane dislocations in SiC toward suppression of bipolar degradation: review and perspective

Kato,

Harada,

Sakane

2024

Jpn. J. Appl. Phys.

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Non-Destructive Quantification of In-Plane Depth Distribution of Sub-Surface Damage on 4H-SiC Wafers Using Laser Light Scattering

Dojima,

Shigematsu,

Tayake

et al. 2024

DDF

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The development of non-destructive quantitative evaluation techniques for the in-plane depth distribution of sub-surface damage (SSD) layer induced by mechanical processing of chemical mechanical polishing (CMP) finished SiC wafers is essential to reduce the occurrence of crystal defects during epitaxial growth. Until now, no wafer inspection method has been able to nondestructively and quantitatively assess the in-plane depth distribution of the SSD. This study investigates the correlation between the scattered light intensity measured nondestructively by the Laser light scattering (LLS) method and the SSD depth estimated by destructive inspection using the Dynamic AGE-ing® method, a sublimation-controlled etching and growth process, to develop a novel non-destructive SSD inspection method. As a result, it was found that there is an exponential relationship between the scattered light intensity by the LLS method on the bare wafer surface and the depth of the SSD layer that contributes to the formation of in-grown stacking faults (IGSF) during subsequent epitaxial growth. The results show that SiC wafer inspection using the novel LLS method, which introduces this relational equation, enables non-destructive and quantitative evaluation of SSD depth and in-plane distribution.

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A Novel Contactless SiC Wafer Planarization Processing after Mechanical Slicing by Dynamic Thermal Annealing Processes

Toda,

Kakutani,

Dojima

et al. 2024

MSF

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In conventional machining of SiC wafers, material loss and sub-surface damage (SSD) of both the front and back surfaces are major issues. In this study, we focused on Dynamic AGE-ing® (DA), which is a sublimation-controlled process, and applied it to the total wafering process without any mechanical contact of both the front and back surfaces to explore the possibilities to reach the CMP-equivalent quality. DA process enables material lossless planarization of SiC wafers by applying a temperature gradient to achieve simultaneous etching and growth at the same rate on one and the other surfaces, respectively. To drive the planarization function for a multi-wire saw finished as-sliced wafer, as an example, a high-temperature regime above 2000 °C under an Ar background pressure higher than 1 kPa to suppress etching and growth rates was employed as the first step in the DA treatment. In this step, an effective annealing function arises where sublimation and recrystallization occur simultaneously through a sub-surface region on both sides of the wafer. Due to the active interchange of the surface and subsurface layer, a self-organizing planarization effect occurs on a macroscopic scale on both surfaces with the removal of SSD. The conventional DA processes were employed for the following microscopic flatness control. As a result, the roughness of the 6-inch as-sliced wafer was reduced to 0.7 nm on the Si-face and 2.0 nm on the C-face while maintaining the wafer thickness. This is the first promising result exhibiting the potential of thermal contactless treatment for next-generation wafer manufacturing by improving quality and cost.

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4H-SiC Full Wafer Mapping Image of CMP-Finished Sub-Surface Damage by Laser Light Scattering

Cited by 3 publications

References 10 publications

Effects of proton implantation for expansion of basal plane dislocations in SiC toward suppression of bipolar degradation: review and perspective

Effects of proton implantation for expansion of basal plane dislocations in SiC toward suppression of bipolar degradation: review and perspective

Non-Destructive Quantification of In-Plane Depth Distribution of Sub-Surface Damage on 4H-SiC Wafers Using Laser Light Scattering

A Novel Contactless SiC Wafer Planarization Processing after Mechanical Slicing by Dynamic Thermal Annealing Processes

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