45 nm-node BEOL integration featuring porous-ultra-low-k/Cu multilevel interconnects

Sugiura, Iwao; Nakata, Yoshihiro; Misawa, N.; Otsuka, Shun; Nishikawa, Naofumi; Iba, Yoshihisa; Sugimoto, Fumitoshi; Setta, Yuji; Sakai, Hiroshi; Mizushima, Y.; Kotaka, Yasutoshi; Uchibori, Chihiro J.; Suzuki, Takashi; Kitada, Hideki; Koura, Y.; Nakano, K.; Karasawa, T.; Ohkura, Y.; Watatani, H.; Sato, Motonobu; Nakai, S.; Nakaishi, Masafumi; Fukuyama, S.; Miyajima, M.; Nakamura, Tomoji; Yano, Ei; Watanabe, Keiji

doi:10.1109/iitc.2005.1499906

Cited by 13 publications

(5 citation statements)

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“…3 plots the yield for 0.28-m-pitched lines with 0.14-m-diameter vias as a function of the intentional shift in alignment. The yield with the TF process significantly decreases when the intentional shift in alignment is greater than 0.03 m. These facts prove that the alignment margin in the VF process is larger than that in the TF [7], [8]. Most research, however, has investigated the TF process with HM processes to eliminate the ashing damage done to organic low-films such as SiLK and FLARE [9]- [13], but the VF process using HMs has not been proposed especially for SiOCH-based low-films.…”

Section: Introductionmentioning

confidence: 69%

Robust Cu Dual Damascene Interconnects With Porous SiOCH Films Fabricated by Low-Damage Multi-Hard-Mask Etching Technology

Ohtake

Tsuji

Tada

et al. 2006

IEEE Trans. Semicond. Manufact.

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Low-damage hard-mask (HM) plasma-etching technology for porous SiOCH film ( = 2 6) has been developed for robust 65-nm-node Cu dual damascene interconnects (DDIs). No damage is introduced by fluorocarbon plasma etching irrespective of whether rigid ( = 2 9) or porous ( = 2 6) SiOCH films are used, due to the protective CF-polymer layer deposited on the etched sidewall. The etching selectivity of the SiOCH films to the inorganic HMs is kept high by controlling the radical ratio of carbon relative to oxygen in the etching plasma gas. However, oxidation damage penetrates the films from the sidewalls due to the O 2 plasma used for photoresist ashing. This damage is increased by the porous structure. As a result, we developed a via-first multihard-mask process for the DD structure in porous SiOCH film with no exposure to O 2 -ashing plasma, and we controlled the via-taper angle by RF bias during etching. We fabricated robust Cu DDIs with tapered vias in porous SiOCH film that can be applied to 65-nm-node ULSIs and beyond.Index Terms-Author, please supply your own keywords or send a blank e-mail to keywords@ieee.org to receive a list of suggested keywords.

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Section: Introductionmentioning

confidence: 69%

Robust Cu Dual Damascene Interconnects With Porous SiOCH Films Fabricated by Low-Damage Multi-Hard-Mask Etching Technology

Ohtake

Tsuji

Tada

et al. 2006

IEEE Trans. Semicond. Manufact.

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“…Another example to show the strong dependency on the tool/material/process capability and readiness is the across-the-wafer non-uniformity of modern CMP tools which so far seem unable to support the Hard Mask Retention scheme for the use of ULK at the trench level for the 65 nm node BEOL technologies in the manufacturing phase, although a bunch of damascene schemes have been reported [18][19][20][21][22][23][24].. Thus, discussions on possibility of implementation of ULK in the 45 nm node BEOL must be made on certain assumptions about the tool capability/readiness and limitation for manufacturing [25][26][27]. Figure 14 lists possible damascene schemes for the 45 nm node shown together with their necessary technical breakthroughs and their attainable k eff 's.…”

Section: Technical Challenges To the 45 Nm Beol Processmentioning

confidence: 97%

Low-k/copper integration scheme suitable for ULSI manufacturing from 90nm to 45nm nodes

Nogami

Lane²,

Fukasawa

et al. 2005

SPIE Proceedings

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This paper discusses low-k/copper integration schemes which has been in production in the 90 nm node, have been developed in the 65 nm node, and should be taken in the 45 nm node. While our baseline 65 nm BEOL process has been developed by extension and simple shrinkage of our PECVD SiCOH integration which has been in production in the 90 nm node with our SiCOH film having k=3.0, the 65 nm SiCOH integration has two other options to go to extend to lower capacitance. One is to add porosity to become ultra low-k (ULK). The other is to stay with low-k SiCOH, which is modified to have a "lower-k". The effective k-value attained with the lower-k (k=2.8) SiCOH processed in the "Direct CMP" scheme is very close to that with an ULK (k=2.5) SiCOH film built with the "Hard Mask Retention" scheme. This paper first describes consideration of these two damascene schemes, whose comparison leads to the conclusion that the lower-k SiCOH integration can have more advantages in terms of process simplicity and extendibility of our 90 nm scheme under certain assumptions. Then describing the k=2.8 SiCOH film development and its successful integration, damascene schemes for 45nm nodes are discussed based on our learning from development of the lower-k 65nm scheme. Capability of modern dry etchers to define the finer patterns, nonuniformity of CMP, and susceptibility to plasma and mechanical strength and adhesion of ULK are discussed as factors to hamper the applicability of ULK.

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“…In this study, first the number of interconnect layer for FEA was increased from two· to four t6 find the effect of mechanical properties of dielectrics on CPI, since the actual interconnect structure for the 65nm technology node will have more than 11 layers with complex geometry and material combinations [8]. The four-level sub-modeling technique was used to link the mechanical deformation from the package level to the interconnect level and the modified virtual crack closure (MVCC) technique [9] was used to calculate the ERR.…”

Section: Introductionmentioning

confidence: 99%

Chip Package Interaction analysis for Cu/Ultra low-k large die Flip Chip Ball Grid Array

Uchibori

Lee

Zhang

et al. 2008

2008 IEEE 9th VLSI Packaging Workshop of Japan

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The impact of Chip-Package Interaction (CPI) which is caused by the mismatch in the coefficient of thermal expansion (CTE) between substrate and chip in a Flip Chip Ball Grid Array (FCBOA) on the mechanical reliability of Cu/Ultra low-k in a larger die was investigated using Finite Element Analysis (FEA). In order to associate the deformation and thermal stresses in FCBOA with those in the Cu/Ultra low-k structure which has a large difference of dimension, multi-step sub-modeling technique was used. The energy release rate (ERR) which indicates the driving force for delamination at the specific interfaces in Cu/Ultra low-k structures was calculated using modified virtual crack closure (MVCC) method to assess the mechanical reliability. The ERR at the different interfaces in four metal layers (M1 to M4) model were calculated to find the effect of mechanical properties of dielectrics on CPI. The ERR at the interface in the upper layer was higher than that at the lower layer, when ultra low-k is used in M1 and M2 layers and SiOC is used in M3 and M4 layers. However, the ERR at M4 interface becomes about 33% lower when Si0 2 is used in M4 level. This result indicates that the mechanical properties of dielectrics are important to control CPI. Then, the ERR of nine metal layers (M1 to M9) model was calculated to improve the accuracy of simulations where the dimension of interconnect structures were determined by the design rule for 90nm technology node. In this model, the ERR at M9 layer decreased significantly with W trench between Al pad and M8 layer which indicates that the interconnect structure affects the CPI. Finally, the bump layout impacts on CPI were investigated. The highest equivalent stress near the under bump material (UBM) of the outer most solder bump was reduced about 20% by placing two extra solder bumps next to it. This result indicates that the layout of solder bump affects CPI, as well. Based on these study, the guideline to improve the mechanical reliability of Cu/Ultra low-k Interconnect in FCBOA by the material selection for interconnect and by optimizing the interconnect structure and the bump layout will be discussed.

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45 nm-node BEOL integration featuring porous-ultra-low-k/Cu multilevel interconnects

Cited by 13 publications

References 0 publications

Robust Cu Dual Damascene Interconnects With Porous SiOCH Films Fabricated by Low-Damage Multi-Hard-Mask Etching Technology

Robust Cu Dual Damascene Interconnects With Porous SiOCH Films Fabricated by Low-Damage Multi-Hard-Mask Etching Technology

Low-k/copper integration scheme suitable for ULSI manufacturing from 90nm to 45nm nodes

Chip Package Interaction analysis for Cu/Ultra low-k large die Flip Chip Ball Grid Array

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