45-nm gate length CMOS technology and beyond using steep halo

Abstract

45-nm CMOS devices with a steep halo using a highramprate spike annealing (HRR-SA) are demonstrated with drive currents of 697 and 292 pA/pm for an off current less than 10 nA/pm at 1.2 V. For an off current less than 300 nA/pm, 33-nm pMOSFETs have a high drive current of 403 pA/pm at 1.2 V. In order to fabricate a steeper halo than these MOSFETs, a source/drain extension (SDE) activation using the HRR-SA process was performed after a deep source/drain (S/D) formation. By using this sequence defined as a reverse-order S/D formation, 24-nm nMOSFETs are achieved with a high drive current of 796 pA/pm for an off current less than 300 nA/pm at 1.2 V.

Sub-40 nm SOI V-groove n-MOSFETs

“…In contrast to the results from Kedzierski and co-workers [3] on thin body MOSFETs, our V-groove approach does not suffer from high source (or drain) to channel contact resistances. Subthreshold slope and off-current of our devices are very comparable to those published by Wakabayashi and co-workers [2]. However, as pointed out above, our device design has the freedom to reduce the body thickness for smaller source/drain separations which is expected to substantially improve S as well as .…”

“…Table I displays a selected number of electrical characteristics for devices with channel lengths between 15 nm and 36 nm. It is obvious from both, the transconductance data as well as the drive current values that our data compare well with state-of-the-art classical approaches [1], [2]. In contrast to the results from Kedzierski and co-workers [3] on thin body MOSFETs, our V-groove approach does not suffer from high source (or drain) to channel contact resistances.…”

Ballistic/quasi-ballistic transport in nanoscale transistor

“…The index of ballisticity b is distributed between 0.2 and 0.7, well below the ballistic limit [10][11][12][13]. Notice that the smaller device shows a worse value of index b.…”

Degradation of current drivability of Schottky barrier source/drain transistors induced by high-k gate dielectrics and possible measures to suppress the phenomenon

“…As a result of this trend toward miniaturization, many devices with a gate electrode shorter than 100 nm have been reported and even normal operation of sub-10 nm gate length devices at room temperature has been reported [1][2][3][4][5][6][7]. According to this trend, quite high current drivability under low power supply voltage is required for transistors.…”