40 Gbit/s optical communications: InP DHBT technology, circuits and system experiments

Godin, J.; André, Ph.; Benchimol, J.L.; Berdaguer, P.; Blayac, S.; Burie, J.-R.; Desrousseaux, P.; Duchenois, A.M.; Kauffmann, N.; Konczykowska, A.; Riet, M.

doi:10.1109/gaas.1999.803754

Cited by 6 publications

(3 citation statements)

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“…High performance InP/InGaAs DHBT's grown by chemical beam epitaxy (CBE) have been reported with 180 GHz f T , 185 GHz f MAX , a gain of 50 at a current density of 1x105 A.cm -2 , a breakdown voltage>5 V [1]. These features are required for circuits found in 40 Gb/s IC's.…”

Section: Introductionmentioning

confidence: 99%

Self Heating in InP DHBT Technology for 40 Gb/s ICs

Giguerre

Abboun²,

Aniel

et al. 2002

32nd European Solid-State Device Research Conference

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Self heating is investigated in InP/InGaAs DHBT's, a transistor technology well suited for 40 Gb/s IC's. An original approach associates experiments and simulations. InP DHBT's are shown to heat up even if their I-V characteristics do not present a negative differential output conductance as GaAs HBT's do. Their thermal resistance was found in the same range of values both using physical modeling and pulsed measurements coupled with electrical modeling.

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Section: Introductionmentioning

confidence: 99%

Self Heating in InP DHBT Technology for 40 Gb/s ICs

Giguerre

Abboun²,

Aniel

et al. 2002

32nd European Solid-State Device Research Conference

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“…1). As previously described [4], the transistors have been fabricated on CBE-grown epitaxial structure, and include a composite InGaAshGaAsPhP collector to minimise the collector current blocking effects, a highly Cdoped graded base and an InP emitter. The use of a graded base eases the HBT scaling and 0-7803-6550-X/00/$10.0002000 IEEE.…”

Section: Technologymentioning

confidence: 99%

Design of a 50 Gbit/s InP/InGaAs HBT master-slave D-type flip-flop

Kasbari

André²,

Blayac³

et al.

8th IEEE International Symposium on High Performance Electron Devices for Microwave and Optoelectronic Applications (Cat. No.00

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The design of a 50 Gbit/s master-slave D-type flip-flop for ETDM transmission system is presented. The chip is fabricated in an InPhGaAs DHBT self-aligned technology with typical Ft and Fmax of about 160 GHz and 210 GHz respectively. We show how our design benefits at best from the available technology. The switching of the transistors is optimised as well as the sizing of basic blocks like emitter-followers or current switches. At this operating frequency, the layout step imposes to take into account propagation phenomena and interconnection parasitic elements, which necessarily degrade the performances. Appropriate methods are systematically applied to evaluate and reduce these effects.

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“…As already described [4], the transistors ( Fig. 1) are fabricated on CBE-grown epitaxial structure, and include an InP emitter, a highly C-doped graded base, and a composite InGaAshGaAsPnnP collector, to minimize the collector current blocking effect.…”

Section: The Improved 1ngaashp Dhbt Technologymentioning

confidence: 99%