2017 IEEE International Solid-State Circuits Conference (ISSCC) 2017
DOI: 10.1109/isscc.2017.7870268
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4.6 A 1/2.3inch 20Mpixel 3-layer stacked CMOS Image Sensor with DRAM

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Cited by 63 publications
(21 citation statements)
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“…With 3D stacking of top-tier SPADs on advanced digital DSM CMOS, pixel pitches below 8 µm are possible. The recent advent of three tier stacking [ 31 ] allowing the interconnection of back-illuminated sensing layer, processing and memory layers will further enhance the dynamic range, frame rate and power of both SPAD-based and CIS-based oversampled image sensors while facilitating novel ISP approaches such as motion tracking and solid-state optical image stabilization [ 28 ].…”
Section: Discussionmentioning
confidence: 99%
“…With 3D stacking of top-tier SPADs on advanced digital DSM CMOS, pixel pitches below 8 µm are possible. The recent advent of three tier stacking [ 31 ] allowing the interconnection of back-illuminated sensing layer, processing and memory layers will further enhance the dynamic range, frame rate and power of both SPAD-based and CIS-based oversampled image sensors while facilitating novel ISP approaches such as motion tracking and solid-state optical image stabilization [ 28 ].…”
Section: Discussionmentioning
confidence: 99%
“…For its sensing element, we emulate the fidelity characteristics of an AR0330 [ 47 ] which is a typical mobile-class image sensor with sufficient number of pixels for providing high-quality images. For its storage element, we emulate the power profile of a 4 Gb LPDDR4 DRAM, which is commonly seen in commercial 3D stacked sensors [ 18 ] for slow-motion video capture. Finally, for its processing element, we emulate the power characteristics of a Myriad2, a vision co-processor found in mobile devices [ 51 , 52 ], capable of neural network processing and feature-based processing, and also Neurostream [ 4 ], another recent candidate architecture for energy-efficient vision processing.…”
Section: Experimental Methodologymentioning
confidence: 99%
“…These imagers still use the traditional CSI interface to communicate with the SoC. For slow-motion capture, Sony [ 18 ] stacks a DRAM beneath the sensor layers. With local memory, the sensor captures and buffers frames at 1000 fps, sending them across the slower camera interface to the host.…”
Section: Background and Related Workmentioning
confidence: 99%
“…Note, with the CMOS-based IS technology, the quality of captured videos using digital cameras has improved significantly. Cameras in new smartphones can record video streams up R f of 960 frames per second (fps) at a resolution of 720p [23]. In addition, there are commercially available high speed cameras with R f of 25.7 kfps and 1 Mfps at resolutions of 1280×800 and 128×32, respectively [24].…”
Section: Introductionmentioning
confidence: 99%