4×, 3‐level, blind ADC‐based receiver

Abstract

The design of a 4× blind analogue-to-digital converter (ADC)-based receiver implemented in 65 nm CMOS technology is presented. The ADC, which has three levels with two adjustable thresholds, effectively implements a speculative decision-feedback equaliser. By reducing the ADC resolution and by simplifying the digital clock and data recovery design, the power consumption is reduced by a factor of 2 compared with previous works. Measurement results confirm a bit error rate of <10 −12 at 5 Gbit/s with a high-frequency jitter tolerance of 0.39 and 0.31 UI pp for a 9.3 and a 12.9 dB FR4 channel, respectively. The entire receiver consumes 63 and 86 mW for the respective channels.