4×25 Gb/s Transceiver With Optical Front-end for 100 GbE System in 65 nm CMOS Technology

Chiang, Po-Jui; Jiang, Jhih-Yu; Hung, Hao-Wei; Wu, Cheng‐Hsun; Chen, Gaun-Sing; Lee, Jri

doi:10.1109/jssc.2014.2365700

Cited by 43 publications

(18 citation statements)

References 4 publications

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“…Fig. 11 also shows calculated input-referred equivalent noise-current using (12) as well as simulated input-referred equivalent noise-current of a more complete small-signal model, which includes all gate-drain and gate-source capacitances, biasing resistor, , in Fig. 6, and bond pads.…”

Section: Measurement Resultsmentioning

confidence: 99%

“…Other transimpedance limit enhancement techniques include inductive peaking [7]- [12], distributed TIAs [13], [14], and recent multi-path inductorless TIAs [15]. There are also modifications to the conventional RGC TIA that address some of its shortcomings and improve the transimpedance limit with power-and area-efficient bandwidth extension.…”

Section: Introductionmentioning

confidence: 99%

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10-Gb/s 0.13-<formula formulatype="inline"> <tex Notation="TeX">$\mu{\rm m}$</tex></formula> CMOS Inductorless Modified-RGC Transimpedance Amplifier

Taghavi

Belostotski

Haslett

et al. 2015

IEEE Trans. Circuits Syst. I

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This paper presents an inductorless 0.13-CMOS TIA structure that is a modified version of a regulated cascode (RGC) TIA. An immittance converter is incorporated to reduce power consumption while increasing transimpedance gain. Measured 3-dB bandwidth is 7 GHz, sufficient for 10-Gb/s operation, in the presence of 250 fF capacitance at the TIA input, representative of typical CMOS photodiode capacitance. The transimpedance gain of the single-stage TIA is 50 , and the group-delay variation is less than 19 ps over the 3-dB bandwidth. The circuit occupies an active area of and consumes 7 mW from a 1.5-V supply. The measured average input-referred current noise of the TIA is 31. Simulations and analysis show that the proposed single-stage TIA architecture is capable of achieving improvement in the transimpedance limit over a single-stage RGC TIA designed for the same data rate and the same input photodiode capacitance. A comparison of measurement results to published TIAs also demonstrates the competitive performance of the proposed TIA in terms of the TIA transimpendance gain, bandwidth, area, and power consumption. in 2011. He is currently working toward his Ph.D. degree at the University of Calgary. His research activity is focused on RF circuits and systems, including delay circuits and RF beamforming. Currently, he is conducting research on first-and second-order all-pass filters and their applications and on the design and fabrication of wideband spatial beamformers.

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Section: Measurement Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

10-Gb/s 0.13-<formula formulatype="inline"> <tex Notation="TeX">$\mu{\rm m}$</tex></formula> CMOS Inductorless Modified-RGC Transimpedance Amplifier

Taghavi

Belostotski

Haslett

et al. 2015

IEEE Trans. Circuits Syst. I

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“…Figure 26 a illustrates a traditional TIA implementation which was first demonstrated with CMOS technology in [ 76 ] and achieved 1-Gb/s operation. This topology has been widely used and has succeeded in achieving high-speed operations of 10 and 25 Gb/s [ 44 , 77 ]. Alternatively, as shown in Figure 26 b, the combination of a common-source amplifier, a source follower, and a feedback resistor has been commonly employed to provide a low output impedance [ 78 , 79 , 80 ].…”

Section: Cmos Transimpedance Amplifier (Tia)mentioning

confidence: 99%

“…In [ 44 ], the fabrication of an optical TX in 0.13-µm technology is also provided, and the overall power consumption of the transmitter and the receiver is 1.25 W per channel. In [ 77 , 124 ], a National Taiwan University group achieved a data rate of 25 Gb/s per channel using a similar structure. In order to overcome the limited speed of the conventional linear phase detector in [ 44 ], the studies in [ 77 , 124 ] replaced the conventional linear phase detector with a mixer-based phase detector.…”

Section: Clock and Data Recovery (Cdr) Circuitsmentioning

confidence: 99%

Review of CMOS Integrated Circuit Technologies for High-Speed Photo-Detection

Jeong

Bae

Jeong

2017

Sensors

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The bandwidth requirement of wireline communications has increased exponentially because of the ever-increasing demand for data centers and high-performance computing systems. However, it becomes difficult to satisfy the requirement with legacy electrical links which suffer from frequency-dependent losses due to skin effects, dielectric losses, channel reflections, and crosstalk, resulting in a severe bandwidth limitation. In order to overcome this challenge, it is necessary to introduce optical communication technology, which has been mainly used for long-reach communications, such as long-haul networks and metropolitan area networks, to the medium- and short-reach communication systems. However, there still remain important issues to be resolved to facilitate the adoption of the optical technologies. The most critical challenges are the energy efficiency and the cost competitiveness as compared to the legacy copper-based electrical communications. One possible solution is silicon photonics which has long been investigated by a number of research groups. Despite inherent incompatibility of silicon with the photonic world, silicon photonics is promising and is the only solution that can leverage the mature complementary metal-oxide-semiconductor (CMOS) technologies. Silicon photonics can be utilized in not only wireline communications but also countless sensor applications. This paper introduces a brief review of silicon photonics first and subsequently describes the history, overview, and categorization of the CMOS IC technology for high-speed photo-detection without enumerating the complex circuital expressions and terminologies.

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“…Equalizer being the major power dissipating block in a coherent optical receiver [17], we studied analog domain implementation of the equalizer as a proof-of-concept validation of the analog processing based transceiver. It may also be seen from the literature that analog domain processing is an attractive choice for low-power equalization in various types of high-speed links [18][19][20][21][22][23][24][25][26][27]. Specifically for optical links, a CMOS receiver with a continuous-time linear equalizer for 30 Gb/s links is reported in [26] and a monolithic optoelectronic IC designed in a 130 nm CMOS process that uses analog domain slope detection based adaptive equalizer is demonstrated in [27] for links with a carrier of 850 nm wavelength.…”

Section: Introductionmentioning

confidence: 99%

All-Analog Adaptive Equalizer for Coherent Data Center Interconnects

Nambath

Ashok

Manikandan

et al. 2020

J. Lightwave Technol.

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We present the detailed architecture of an allanalog adaptive equalizer for low-power analog signal processing based coherent optical dual-polarization quadrature phase-shift keying transceivers. The proof of concept equalizer uses the constant modulus algorithm for weight coefficient update. The equalizer, implemented in a 130 nm SiGe BiCMOS technology for 100 Gb/s operation, occupies ∼1.4 mm × 1.35 mm area and draws 1 A current from a 2.5 V supply. Its functionality is validated experimentally for data rates up to 40 Gb/s and by using postlayout circuit simulations for data rates up to 100 Gb/s. The equalizer output after processing with a behavioral Costas loopbased carrier phase recovery and compensation module shows bit error rates well within the hard-decision forward error correction limit for 40 Gb/s single-mode fiber links of length up to 10 km. Performance and power consumption of the equalizer are expected to improve when implemented in advanced CMOS or FinFET technologies. The simple architecture of the analog domain equalizer makes it suitable for analog coherent shortreach interconnects with length less than 10 km and carrier wavelengths of either 1310 nm or 1550 nm.

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4×25 Gb/s Transceiver With Optical Front-end for 100 GbE System in 65 nm CMOS Technology

Cited by 43 publications

References 4 publications

10-Gb/s 0.13-<formula formulatype="inline"> <tex Notation="TeX">$\mu{\rm m}$</tex></formula> CMOS Inductorless Modified-RGC Transimpedance Amplifier

10-Gb/s 0.13-<formula formulatype="inline"> <tex Notation="TeX">$\mu{\rm m}$</tex></formula> CMOS Inductorless Modified-RGC Transimpedance Amplifier

Review of CMOS Integrated Circuit Technologies for High-Speed Photo-Detection

All-Analog Adaptive Equalizer for Coherent Data Center Interconnects

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