2015
DOI: 10.1109/tcsi.2015.2440732
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10-Gb/s 0.13-<formula formulatype="inline"> <tex Notation="TeX">$\mu{\rm m}$</tex></formula> CMOS Inductorless Modified-RGC Transimpedance Amplifier

Abstract: This paper presents an inductorless 0.13-CMOS TIA structure that is a modified version of a regulated cascode (RGC) TIA. An immittance converter is incorporated to reduce power consumption while increasing transimpedance gain. Measured 3-dB bandwidth is 7 GHz, sufficient for 10-Gb/s operation, in the presence of 250 fF capacitance at the TIA input, representative of typical CMOS photodiode capacitance. The transimpedance gain of the single-stage TIA is 50 , and the group-delay variation is less than 19 ps over… Show more

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Cited by 56 publications
(8 citation statements)
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“…FoMs are used to allow us to make a fair comparison. In terms of FOM1, Kim and Buckwalter 19 and Taghavi 21 seem to show a better performance, but when taking more parameters into account, our design demonstrates significant superiority in terms of FOM2.…”
Section: The Optical Receivermentioning
confidence: 81%
“…FoMs are used to allow us to make a fair comparison. In terms of FOM1, Kim and Buckwalter 19 and Taghavi 21 seem to show a better performance, but when taking more parameters into account, our design demonstrates significant superiority in terms of FOM2.…”
Section: The Optical Receivermentioning
confidence: 81%
“…The proposed circuit performance is summarized in Table 2 and compared with other wideband TIAs. The core MIC structure 16 and modified MIC structure 17 have almost the same gain behavior compared to the proposed structure and higher bandwidth. Note that inductor have been used in Hosseini et al 17 to extend bandwidth, and both works have considered smaller PD capacitance.…”
Section: Circuit Design and Verificationmentioning
confidence: 85%
“…However, to avoid the negative input resistance and preserve stability, the value of R L must be kept low which limits the gain. An improved version of this circuit is presented in Taghavi et al, 16 which can achieve very small input impedance by combining the cross‐coupled and regulated cascode structures. Called the immittance converter, this structure is shown in Figure 1D, which employs two feedback loops, and M 2 provides a summation of these two loops.…”
Section: Introductionmentioning
confidence: 99%
“…Some of the latest works proposed the regulated cascode (RGC) topology as the core of a fast TIA ASIC chip [14,[21][22][23]. As shown in figure 1(a), the RGC topology exhibits a transimpedance gain that is approximately proportional to the resistive load at the output node, that is, 𝑍 𝑇 ,𝑅𝐺𝐶 ≈ 𝑅 2 .…”
Section: Comparison Between Fvf and Rgc Topologymentioning
confidence: 99%